TYAN S1846 User Manual page 51

This option specifies the length of a delay inserted between consecutive 16-bit
I/O operations. The settings are Disabled and from 1 to 4 Sysclk (system
clocks) in increments of one.
PIIX4 SERR#
Set this option to Enabled to enable the SERR# signal for the Intel PIIX4 chip.
The settings are Enabled or Disabled.
USB Passive Release
Set this option to Enabled to enable passive release for USB. The settings are
Enabled or Disabled.
PIIX4 Passive Release
Set this option to Enabled to enable passive release for the Intel PIIX4e chip.
This option must be Enabled to provide PCI 2.1 compliance. The settings are
Enabled or Disabled.
PIIX4 DELAYED TRANSACTION
Set this option to Enabled to enable delayed transactions for the Intel PIIX4
chip. This option must be Enabled to provide PCI 2.1 compliance. The settings
are Enabled or Disabled.
TypeF DMA Buffer Control1 and 2
These options specify the DMA channel where TypeF buffer control is
implemented. The settings are Disabled, Channel-0, Channel-1, Channel-2,
Channel-3, Channel-5, Channel-6, or Channel-7.
DMA-n Type
These options specify the bus that the specified DMA channel can be used
on. The settings are Normal ISA, PC/PCI, or Distributed.
CPU Bus Frequency
This option provides selective CPU bus frequency; however, it is stongly
recommended that the default setting (Auto) be selected. Unpredictable
situations may arise if the Intel default CPU bus speed is not used. The
settings are Auto, 66.8MHz, 68.5MHz, 75MHz, 83.3MHz, 100MHz, 103MHz, or
112MHz.
S1846 Tsunami ATX
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