Denon DN-HS5500 Service Manual page 29

EP2C5Q208C8N (IC103)
.
EP2C5Q208C8N Terminal Function
Pin No Pin name
1 SH_DB27
2 SH_DB28
3 SH_DB29
4 SH_DB30
5 SH_DB31
6 SH_RD
7 VCCIO1
8 PS2DAT OUT
9 GND
10 PS2_INH
11 PS2_PWR
12 SH_CS5
13 SH_IRQa
14 SHAD_TRG
15 SH_IRQb
16 TDO
17 TMS
18 TCK
19 TDI
20 DATA0
21 DCLK
22 nCE
23 SH_CKIO
24 SH_CS6
25 GND
26 nCONFIG
27 PS2DAT
28 PS2CLK
29 VCCIO1
30 LCD_SYNC
31 SH_RDY
32 SCL
33 SH_BS
34 SH_DRQ
35 SH_IRQc
36 SH_CS7
37 SH_DAK
38 GND
I/O Pol
IO 32 bits data bus (CPU)
IO 32 bits data bus (CPU)
IO 32 bits data bus (CPU)
IO 32 bits data bus (CPU)
IO 32 bits data bus (CPU)
I N (CPU: -RD)
VCCIO1
O PS/2 data output (Not used)
GND
O N PS/2 inhibit signal output (Not used)
O PS/2 Power ON/_OFF signal (Not used)
I N LCD, 32 bits bus width (CPU)
O Interrupt request 2 (CPU:PINT2)
O N Non-maskable interrupt request (CPU:NMI)
O Interrupt request 3 (CPU:IRQ1)
TDO
TMS
TCK
TDI
DATA0 Configuration (CPU:TxD2)
DCLK Configuration (CPU:SCK2)
nCE GND
I Master clock: 67.7MHz (CPU:CKIO)
I N TMS32DA710, 16 bits bus width (CPU)
GND
nCONFIG Configuration (CPU:PE1)
I PS/2 data input (Not used)
I PS/2 clock (Not used)
VCCIO1
O Send LCD reading start trigger to CPU (CPU:IRQ0)
O Wait (CPU:-WAIT)
IO N IIC clock line L
I N (CPU:-BS)
O DMA transfer request (CPU:DRQ0)
O Interrupt request 3 (PS/2 to CPU:PINT3)
I N LCD, IDE, PANEL, PS/2, FPGA 32 bits bus width (CPU)
I DMA transfer accept (CPU:DACK0)
GND
DN-HS5500
Function
29