Pin Description - Denon DN-HS5500 Service Manual

W9812G6GH-6 (IC104, 105, 502, 503)

PIN DESCRIPTION

PIN NUMBER
23 - 26, 22,
29 - 35
20, 21
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
19
18
17
16
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
V 1
CC
2
DQ0
3
V Q
CC
DQ1 4
5
DQ2
6
V Q
SS
DQ3 7
DQ4
8
V Q
9
CC
DQ5 10
DQ6 11
V Q
12
SS
DQ7 13
V 14
CC
LDQM 15
16
WE
CAS 17
RAS 18
CS 19
20
BS0
BS1 21
A10/AP
22
A0
23
24
A1
25
A2
26
A3
27
Vcc
PIN NAME FUNCTION
A0 - A11 Address
BS0, BS1 Bank Select
DQ0 - Data Input/
DQ5 Output
Chip Select
CS
Roe Address
RAS
Strobe
Column Address
CAS
Strobe
Write Enable
WE
UDQM/ Input/Output
LDQM Mask
CLK Clock Inputs
CKE Clock Enable
Vcc Power (+3.3V)
Vss Ground
Power (+3.3V)
VccQ
for I/O Buffer
Ground for I/O
VssQ
Buffer
NC No Connection
39
DN-HS5500
54 V
SS
53
DQ15
52
VssQ
51 DQ14
50
DQ13
49
V Q
CC
48 DQ12
DQ11
47
V Q
46
SS
45 DQ10
44 DQ9
V Q
43
CC
42 DQ8
41 V
SS
40 NC
39 UDQM
38 CLK
CKE
37
36 NC
35
A11
34 A9
33 A8
32 A7
31 A6
30 A5
29
A4
28
Vss
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 - A11. Column address: A0 - A8.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input, When sampled at the rising edge of
the clock, RAS, CAS and WE define the operation
to be executed.
Referred to RAS
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from Vcc, used for output buffers to
improve noise.
Separated power from Vss, used for output buffers to
improve noise.
No Connection