Denon DN-HS5500 Service Manual page 38

ISP1761BE (IC403)
Block Diagram
37 to 39, 41 to 43,
45 to 47, 49, 51,
52, 54, 56 to 58,
60 to 62, 64 to 66,
68 to 70, 72 to 74,
76 to 78, 80
D[15:0]/D[31:0]
82, 84, 86, 87,
89, 91 to 93,
95 to 98,
100 to 103, 105
17
A[17:1]
CS_N 106
RD_N
107
WR_N
108
DC_IRQ
111
HC_IRQ
112
DC_DREQ
113
HC_DREQ
114
HC_DACK
116
DC_DACK
117
124
C_B
125
C_A
126
V
CC(C_IN)
8
GND(OSC)
16
RREF1
GND
(RREF1)
102
103
pin 1 index
128
1
V
CC(I/O)
10, 40, 48, 59, 67,
75, 83, 94, 104, 115
BUS INTERFACE:
MEMORY
MANAGEMENT
UNIT
+
SLAVE DMA
CONTROLLER
+
INTERRUPT
CONTROL
REGISTERS
SUPPORT
TRANSACTION
CHARGE
TRANSLATOR
PUMP
(TT) AND RAM
OTG CONTROLLER
DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC
HI-SPEED HI-SPEED
USB ATX2
USB ATX1
15 20 19 18 21 127 23 22 27
RREF2
DP1 DM1 DP2
GNDA GND GNDA
OC1_N/
(RREF2)
V
BUS
PSW1_N
ISP1761BE
30 MHz
SEL16/32
60 MHz
HC PTD
MEMORY
(3 kB)
HC PAYLOAD DC BUFFER
MEMORY MEMORY
(60 kB) 8 KBYTES
MEMORY ARBITER
AND FIFO
ADVANCED
ADVANCED
PHILIPS
PERIPHERAL
SLAVE HOST
CONTROLLER
CONTROLLER
HI-SPEED
USB ATX3
26 25 28 128 30 29 34 33 32
DM2 DM3
RREF3 DP3
OC2_N GNDA
GND
(RREF3)
PSW2_N
PSW3_N
38
DN-HS5500
65
64
39
38
11
XTAL1
12
PLL
XTAL2
13
CLKIN
122
RESET_N
GLOBAL CONTROL
119
HC_SUSPEND/
AND POWER
WAKEUP_N
MANAGEMENT
120
DC_SUSPEND/
WAKEUP_N
POWER-ON
110
BAT_ON_N
RESET AND
V ON
BAT
5, 50,
85, 118
5 V-TO-1.8 V REG1V8
VOLTAGE
6, 7
REGULATOR
V
CC(5V0)
5 V-TO-3.3 V
VOLTAGE
9
REG3V3
REGULATOR
DIGITAL
2
AND ANALOG
REF5V
OVERCURRENT
PROTECTION
3
ID
4, 17, 24,
31, 123
GNDA
53, 88, 121
GNDC
14, 36, 44, 55, 63,
71, 79, 90, 99, 109
35 1
004aaa450
GNDD
OC3_N