Denon DN-HS5500 Service Manual page 36

Pin No. Pin Name Symbol
66 PE13 AMUTE
67 -CS0 CS0
68 -CS1 CS1
69 SCK2 CFGCLK
70 DREQ3 DREQ3
71 PINT7 PINT7
72 SDA HIICDAT
73 SCL HIICCLK
74 -BS SHBS
75 DREQ0 DREQ0
76 PVcc V3SH
77 PVss D_GND
78 Vss D_GND
79 Vcc V1SH
80 PE3 PE3
81 TxD0 TxD0
82 -CS6 CS6
83 PE1 CONFIG
84 -CS7 CS7
85 RxD0 RxD0
86 PE4 PE4
87 DREQ1 DREQ1
88 DACK0 DACK0
89 AVss D_GND
90 AN0 AN0
91 AN1 D_GND
92 AN2 D_GND
93 AN3 D_GND
94 AN4 D_GND
95 AN5 D_GND
96 AN6 LCDVCON
97 AN7 MPSD
98 Avref +3.3V
99 Avcc +3.3V
100 TxD2 CFGDAT
101 Vcc V1SH
102 Vss D_GND
103 RxD3 RxD3
104 -ASEBRKAK -ASEBRKAK
105 TxD3 -
106 -WDTOVF -
107 ASEBCK -
108 PVcc V3SH
109 PINT3 PINT3
110 TCK TCK
111 -TRST -TRSET
112 TDI TDI
113 PVss D_GND
114 Vss D_GND
115 Vcc V1SH
116 TMS TMS
117 PVcc V3SH
118 PVss D_GND
119 -ASEMD -ASEMD
120 TDO TDO
121 D31 ..SHDB31
122 D30 ..SHDB30
123 D29 ..SHDB29
124 D28 ..SHDB28
125 PVcc V3SH
126 PVss D_GND
127 D27 ..SHDB27
128 D26 ..SHDB26
129 D25 ..SHDB25
130 D24 ..SHDB24
131 PVcc V3SH
132 D23 ..SHDB23
I/O DET Ext Ini
O -
O -
O -
O -
-
I -
I/O -
I/O -
O -
I -
I - - -
- - - -
- - - -
I - - -
O -
O -
O -
O -
O -
I -
I/O -
I -
O -
- - - -
I -
I -
- - - -
- - - -
- - - -
- - - -
O -
O -
I -
I -
O -
I - - -
- - - -
I -
O -
-
-
-
I - - -
-
I -
I -
I -
- - - -
- - - -
I - - -
I -
I - - -
- - - -
I -
O -
I/O - - -
I/O - - -
I/O - - -
I/O - - -
I - - -
- - - -
I/O - - -
I/O - - -
I/O - - -
I/O - - -
I - - -
I/O - - -
36
DN-HS5500
Res Function
Analog MUTE
External memory chip select 0
External memory chip select 1
Serial clock output (FPGA CFG CLK)
Not used
LCD synchronized read trigger
IIC serial data input/output
IIC serial data clock input/output
Bus-cycle start signal
Direct memory access transfer request 0
- I/O supply (+3.3V)
- GND
- GND
- Core supply (+1.2V)
FPGA configuration status signal
D-Sync output
External chip select 6
Configuration L → H configuration start
External chip select 7
D-Sync input
Configuration done
Direct memory access transfer request 1
Direct memory access request answer 0
- GND
Slid VR PANEL 1 data input for pitch
Not used
- GND
- GND
- GND
- GND
LCD cont.
DD motor engine speed control
Analog reference voltage for A/D converter
Analog power supply for A/D converter
Configuration data
- Core supply (+1.2V)
- GND
Not used
Break acknowledge for emulator (for debug)
Not used
Not used
Not used
- I/O supply (+3.3V)
PS2 data communication interrupt
Test clock input (for debug)
Test reset input (for debug)
Test data input (for debug)
- GND
- GND
- Core supply (+1.2V)
Test mode select input (for debug)
- I/O supply (+3.3V)
- GND
Debug mode enable input (for debug)
Test data output (for debug)
- Data bus 31
- Data bus 30
- Data bus 29
- Data bus 28
- I/O supply (+3.3V)
- GND
- Data bus 27
- Data bus 26
- Data bus 25
- Data bus 24
- I/O supply (+3.3V)
- Data bus 23