Denon DN-HS5500 Service Manual page 34

SH72060W200FPV Block Diagram
SH-2A
CPU core
Instruction
Cache
cache memory
controller
8 Kbytes
Bus state
controller
(BSC)
Port
External bus input/output
External bus width mode input
Pin function
controller
I/O ports
(PFC)
General input/output
High-performance
Power-down
user debugging
interface
(H-UDI)
Port
JTAG input/output
Operand
On-chip RAM
cache memory
128 Kbytes
8 Kbytes
Peripheral
bus controller
Interrupt
Clock pulse
controller
generator (CPG)
(INTC)
Port Port Port
RES input,
EXTAL input,
MRES input,
XTAL output,
CKIO input/output, NMI input,
Clock mode input
IRQ input,
PINT input,
IRQOUT output
D/A converter
mode
(DAC)
control
Port
Analog output
User break
controller
(UBC)
Direct memory
access controller
(DMAC)
Multi-function
Multi-function
timer pulse
timer pulse
unit 2
unit 2
subset
(MTU2)
(MTU2S)
Port Port
Timer pulse Timer pulse
input/output input/output
2
I C bus
A/D converter
interface 3
(ADC)
(IIC3)
Port Port
2
Analog input, I C bus
ADTRG input input/output
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DN-HS5500
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
UBCTRG output
Internal bus (I bus) (B clock)
DREQ input
DACK output
TEND output
Peripheral bus (P clock)
Port output Compare
enable 2 match timer
(POE2) (CMT)
Port
POE input
Serial
communication Watchdog
interface
timer
with FIFO
(WDT)
(SCIF)
Port Port
WDTOVF output
Serial input/output
CPU bus
(C bus)
(I clock)