Sharp LC-37XD1E Service Manual page 78

LC-37XD1E/RU
19. IC202: RH-IXB682WJZZQ
CDFDM DEMODURATOR
Pin No.
12
62
63
61
64
2
5
6
3
9
10
4,11
1
7
8
21
20
19
18
25,26,27,29,31,32,33,34
36
23
38
40
51
50
49
48
16
14
17,60
58
45
43
42
47
55
53
13,28,39,57
22,35,44,52
15,24,30,37,41,46,54,56,59
Pin Name I/O
RESET I
XTALI I
XTALO O
VCCXTAL1.8 -
GNDXTAL -
DVCCA1.8 -
REFM I
REFP I
VCCA1.8 -
INM I
INP I
GNDA -
DGNDA -
VR I
VCCA3.3 -
SDA I/O
SCL I
SDAT I/O
SCLT I
D7/0 O
CLK_OUT O
STR_OUT O
D/P O
ERROR O
HFECO O
CCLK/HFC1 O
CDATA/HFC2 O
CIQ/HFEC3 O
AGC1 I/O
AGC2 I/O
TEST -
IP0 I
OP0 I/O
LOCK/OP1 I/O
LOCK/OP2 O
AUX_CLK I/O
CS0 I
CS1 I
VDD -
VDD_3.3 -
GND -
1. All input are 3.3V compatible
2. All bidirectional pads 3.3V capable
3. All output are 3.3V capable.
Hardware reset,active low.
Crystal oscillator input/external clock(1.8V).
Crystal oscillator output.
Analog oscillator supply(1.8V)
Analog oscilltor ground.
Analog part digital supply(1.8V)
Internal negative reference.
Internal positive reference.
Analog supply(1.8V).
Negative analog input.
Positive analog input.
Analog ground.
Analog ground.
Reference.
Analog supply(3.3V)
Serial data(open drain)
Serial clock(open drain)
SDA tuner(open drain)
Serial D7,MPEG data.
MPEG byte or bit clock.
MPEG first byte sync.
MPEG data valid/parity.
MPEG packet error.
Hierarchical FEC output bit 0.
Hierarchical FEC output bit 1 or clock for constellation display.
Hierarchical FEC output bit 2 or data for constellation display.
Hierarchical FEC output bit 3 or IQ validation for constellation display.
RF AGC control
IF AGC control
Reserved test mode,must be ground.
General-purpose input port0 and ADC input for RF level monitoring
General-purpose output port0
General-purpose output port1 or lock indicator.
general-purpose output port2 or lock indicator.
Auxiliary clock.
Chip select LSB.
Chip select MSB.
Digital core supply.
Digital IO supply.
5 – 24
Pin Function