Sharp LC-37XD1E Service Manual page 73

P2
H3,H2,G2,H4,G4,E2,E1,E3,
H1,D1,D2,C2,G3,C1,B1,A1
D5,C5,D6,B3,A2,B2,A3,B4,
A4,C6,B5,A5,D7,C7,B6,A6,
B7,A7,D9,C9,B9,A9,B10,C1
1
J3
K4
L4
G1
J4
W1,U4,U2,U1,R2,R1,T2,T1
AB4,Y2,AA1,Y1,W3,U3,W2,
W4
AF3,AD5,AE3,AE5,AF2,Y3,
AA3,AF1
AE18,AE4,AC16,AC12,AE6,
AC11,AC5,AE12
AE20,AD20,AF20,AE19,AC
17,AD18,AD17,AF19
AC22,AF22,AD21,AC21,AE
21,AC18,AC20,AF21,
AF17
AE17
AE16
AF18
AD16
AD26,AB25,AB24,AC25,AE
26,AB23,AE25,AF26,AD25,
AF25,AE24,AF24,AF23,AE2
3
U26,U25,R23,V26,V25,T23,
V24,V23,W26,W25,Y25,Y26
,Y23,AB26,Y24,AC26
T24
T25
T26
R24
R25
P26
R26
P24
P25
B15,A15,D16,C16,B16,B17,
C17,D17
C15
D15
A14
B14
C14
D14
D13
D12
D11
T4, R4, T3,R3
AE1
AC1
AD1
AB1
AF12
EMIRDnotWR O
EMIDATA[15:0] I/O
EMIADDR[25:2] O
notEMIREQGNT O
notEMIACKREQ I
EMIBOOTMODE0 I
EMISDRAMCLK O
EMIFLASHCLK O
PIO0[7:0] I/O
PIO1[7:0] I/O
PIO2[7:0] I/O
PIO3[7:0] I/O
PIO4[7:0] I/O
PIO5[7:0] I/O
SCLK O
PCMDATA1 O
PCMCLK I/O
LRCLK O
SPDIF O
SMIADDR[13:0] O
SMIDATA[15:0] I/O
notSMICS0 O
notSMICS1 O
notSMICAS O
notSMIRAS O
notSMIWE O
SMIMEMCLKIN I
SMIMEMCLKOUT O
SMIDATAML O
SMIDATAMU O
P1284DATA[7:0] I/O
notP1284SELECTIN I/O
notP1284INIT I/O
notP1284FAULT I/O
notP1284AUTOFD I/O
P1284SELECT I/O
P1284PERROR I/O
P1284BUSY I/O
notP1284ACK I/O
notP1284STROBE I/O
INTERRUPT[3:0] I/O
OUTPLEFT O
OUTMLEFT O
OUTPRIGHT O
OUTMRIGHT O
ROUT O
External read/write access indicator. Common to all devices.
External common data bus.
External common address bus
Bus request/grant indicator
Bus grant/request indicator (5 V tolerant)
External power-up port size indicator (5 V tolerant)
SDRAM clock
Peripheral clock
Parallel input/output pin or alternative function (5 V tolerant)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERESET,T1:CIRE-
SET)
(W2:TVRX,W4:TVTX)
(AF3:ASPECT,AD5:IRQ,AA3:GPIO1,AF1:GPIO0)
(AE6:TVSCL,AC11:TVSDA,AC5:I2CSCL,AE12:I2CSDA)
(AE20:27MHzPWM,)
(AD21:RXD,AC21:TXD,AF21:IR)
Serial clock (5 V tolerant)
PCM data out (5 V tolerant)
External PCM clock input or internal PCM clock output (5 V tolerant)
Left/right clock (5 V tolerant)
Digital audio output (5 V tolerant)
SDRAM address bus
SDRAM data bus
SDRAM chip select for 1st SDRAM
SDRAM chip select for 2nd 16 Mbit SDRAM
SDRAM column address strobe
SDRAM row address strobe
SDRAM write enable
SDRAM memory clock input
SDRAM memory clock output
SDRAM data bus lower byte enable
SDRAM data bus upper byte enable
1284 AV data (5 V tolerant)
1284 AV control signals (5 V tolerant)
External interrupts (5 V tolerant)
Left channel, differential positive current output
Left channel, differential negative current output
Right channel, differential positive current output
Right channel, differential negative current output
Red output
5 – 19
LC-37XD1E/RU
EMIRW
EMID[15-
0]
EMIA[23-
2]
(D5,C5=N
C)
NC
EMICLK
NC
NC
NC
NC
TL4027
SPDIF
SMIA[13-
0]
SMID[15-
0]
SMICS
SMICAS
SMIRAS
SMIWE
SMICLK
SMIDQML
SMIDQMI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MODEMI
RQ,
TL4003,
CIIRQ1,
CIIRQ0
LEFTP
LEFTM
RIGHTP
RIGHTM
R