Sharp LC-37XD1E Service Manual page 57

2. IC1905: VHISii9023+-1Q
HDMI RECIEVER
Pin No. Pin Name
144 Q0
143 Q1
142 Q2
141 Q3
140 Q4
137 Q5
136 Q6
133 Q7
132 Q8
131 Q9
130 Q10
129 Q11
126 Q12
125 Q13
124 Q14
123 Q15
119 Q16
118 Q17
117 Q18
116 Q19
113 Q20
112 Q21
111 Q22
110 Q23
1 DE
2 HSYNC
3 VSYNC
121 ODCK
97 XTALIN
96 XTALOUT
88 MCLKOUT
86 SCK
85 WS
84 SDO
78 SPDIF
77 MUTEOUT
104 INT
102 RESET#
32 DSCL0
31 DSDA0
30 DSCL1
29 DSDA1
28 CSCL
27 CSDA
103 SCDT
107 CLK48B
34 R0PWR5V
33 R1PWR5V
101 RSVDL
56 RSVD_A
6,7,8,10, NC
11,12,13,
14,17,18,
19,20,81,
82,93,10
0
87 MCLKIN
9 EVNODD
40 R0XC+
39 R0XC-
44 R0X0+
43 R0X0-
I/O
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O 24-bit Output Pixel Data Bus.
O Data enable.
O Horizontal Sync Output control signal.
O Vertical Syanc Output control signal.
O Output Data Clock.
I Crystal Clock Input.
O Crystal Clock Output.
O Audio Master Clock Output.
O I2S Serial Clock Output.
O I2S Word Select Output.
O I2S Serial Data Output.
O S/PDIF Audio Output
O Mute Audio Output.
O Interrupt Output.
I Reset Pin. Active LOW.
I DDC I2C Clock for Port 0. 5V Tolerant.
Bi-Di DDC I2C Data for Port 0.
I DDC I2C Clock for Port 1. 5V Tolerant.
Bi-Di DDC I2C Data for Port 1.
I Configuration I2C Clock.
Bi-Di Configuration I2C Data.
O Indicates active video at HDMI input port.
Bi-Di Data Bus Latch Enable. 2
I Port 0 Transmitter Detect. 5V Tolerant.
I Port 1 Transmitter Detect. 5V Tolerant.
I Reserved ,must be tied Low.
Bi-Di Reserved Pin, leave unconnected.
- No internal connection.
O Audio Master Clock Input Reference.
O Indicates Even or Odd field for interlaced formats. Polarity programmable in register.
I TMDS input clock pair. HDMI Port 0.
I TMDS input clock pair. HDMI Port 0.
I TMDS input data pair. HDMI Port 0.
I TMDS input data pair. HDMI Port 0.
Pin Function
5V Tolerant.
5V Tolerant.
5V Tolerant.
5V Tolerant.
5V Tolerant.
5 – 3
LC-37XD1E/RU