IC BLOCK DIAGRAM & DESCRIPTION
Terminal
Terminal
I/O
No.
symbols
-
43 XVDD
Power terminal for crystal oscillator
O
44 XOUT
Joining terminal for crystal resonator (16.9344 MHz)
I
45 XIN
-
46 XVSS
Ground terminal for crystal oscillator. Make sure to ground.
O
47 SBSY
Output terminal for synchronizing signals of sub-code clock.
O
48 EFLG
Monitor terminal for 1 bit or 2 bit error correction
O
49 PW
Output terminal for sub-code P, Q, R, S, T, U or W.
O
50 SFSY
Output terminal for synchronizing signals of sub-code frame. When sub-code is stood by, falls.
I
51 SBCK
Input terminal for clock to read out sub-code. Schmitt input (when not used, make sure to ground.)
O
52 FSX
Output terminal for synchronizing signal (7.35 kHz) which is divided from crystal oscillator.
O
53 WRQ
Output terminal for Q output standby of sub-code.
I
54 RWC
Input terminal for read/write control. Schmitt input.
O
55 SQOUT
Output terminal for Q output of sub-code.
I
56 COIN
Input terminal for command from micro-computer.
Input terminal either for clock to take in command input or for clock to take out sub-code from SQOUT.
57 *CQCK
I
Schmitt input.
I
58 *RES
Input terminal for reseting this LSI. Switches to "L" position for a moment at power-on.
O
59 TST11
Output terminal for test. Make sure to open circuit. (Normally "L" output)
O
60 16M
Output terminal of 16.9344 MHz
O
61 4.2M
Output terminal of 4.2336 MHz
I
62 TEST5
Input terminal for test. Pull-down resistor incorporated. Make sure to ground.
I
63 *CS
Input terminal for chip selecting. Pull-down resistor incorporated. Make sure to ground when not controlled.
I
64 TEST1
Input terminal for test. No pull-down resistor. Make sure to ground.
Note: Each power terminal (VDD, VVDD, LVDD, RVDD and XVDD) must be supplyed with the same voltage.
I7001 TA7668BP (PRE AMP W/2ch ALC)
Pre.OUT
& Rec.IN
5
6
Rre.IN
NF.
Pre
Rec
7
Pre.IN
ALC
8
ALC
DET
10
Pre.IN
Pre
Rec
11
Pre.IN
NF.
9
12
Rec.
Pre OUT
DND
& Rec.IN
- 14 -
DESCRIPTION
Rec.
OUT
Mute
Mute
ch
OUT
IN
1
4
3
15
16
Vcc
2
Vs.
13
14
1
Rec.
Mute
Rec.
OUT
OUT
DND
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