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Table of Contents
IC BLOCK DIAGRAM & DESCRIPTION
IC501 LC78622 (Digital Signal Processor)
EFMO
VV
DD
9
1
Slice level
DEFI
Control
10
EFMIN
Syncrnous Detect
22
FSEQ
EFM Demodulation
12
CLV+
CLV
Digital Servo
13
CLV-
14
V/P
PW
49
51
SBCK
Subcode Dxract
47
QCRC
SBSY
SFSY
50
63
CS
WRQ
53
55
SQOUT
CQCK
57
COIN
56
Servo Commander
54
RWC
15 16
17
20
19 58
HFL
TES
TOFF
JP-
JP+
RES
IC601 LA9240M (Servo Signal Processor)
VV
PDO ISET FR
PCK
TAI
SS
6
4
3
5
7
21
2
VCO Clock Oscillator
& Clock Control
C1 C2 Error Detect &
Correct Control Flag
General Ports
18
24 25 26 27 28
29
48
TGL
CONT1
CONT3
CONT5
EMPH
EFLG
CONT2
CONT4
Vcc1
LDS
LDD
BH1 PH1
64
63
62
61
APC
FIN2
1
VCA
2
FIN1
I/V
3
E
BAL
VCA
4
F
5
TB
TE
TE-
6
TE
7
8
TESI
T.SERVO & T.LOGICK
9
SCI
TH
10
11
TA
TD-
12
F.SERVO & F.LOGICK
13
TD
14
JP
TO
15
FD
16
17
18
FD-
FA
TEST2
TEST4
TST11
TEST1
TEST3 TEST5
59 64 11 32 33 62
23
8
2KÅ~8bit
RAM
Interpolalation Mute
Quadruple Over Sampling
X'tal Root
Timing Generator
60 61 46 52 45 44 43
39 41 42
16M
4.2M
FSX
XIN
XV
RV
DD
DD
XV
XOUT
RV
MUTER
SS
SS
LF2
VR REF1 Vcc2
FSS
DRF CE DAT CL CLK
60
59
58
57
56
55
54 53
REF
RF DET
É -com
INTER FACE
SPINDLE SERVO
19
20
21
22
23
24
25
26
27
FA-
FE
FE-
AGND
SP
SPI
SPG
SP-
SPD
SLEQ
- 11 -
RAM Address
Generatorl
Billingual
Digital Out
Digital Attenuator
Digital Filter
1bit DAC
L.P.F
40
37
35
38
36
RCHO
LCHO
MUTEL
LV
DD
LV
SS
DEF
52
51
50
49
48
NC
47
TBC
46
FSC
DGND
45
44
SLI
SLC
43
SLC
42
RFS-
RF Amp
41
RFSM
40
CV+
39
CV-
38
SLOF
37
HFL
TES
36
35
TOFF
34
TGL
33
JP+
SLED SERVO
28
29
30
31
32
SLD
SL-
SL+
JP-
30
C2F
31
DOUT
(NC)
34
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