Parity Generation And Error Detection - Zenith Z-100 Reference Manual

Parity Generation and Error Detection

When a write operation is being processed, the parity generator looks at the 8-bit
data word and determines if an odd number of logical ones (Is) are present
or not. If not, the parity generator places a logical I in the corresponding memory
location of the parity RAM chip of the bank where that piece of data resides.
Upon a read retrieval, the 9-bit word residing at that address is again checked
for odd parity. If a data loss which produces an even number of bits (such as
an error condition) occurs, the parity generator outputs an error signal to interrupt
the processor.
Parity Check/Generation Disabling
To determine the condition of the parity check circuitry, both parity generation
and parity error checking can be disabled by software means by sending appropri-
ate values to the parity disable port at 100H.
Page 6.9
System Memory