Zenith Z-100 Reference Manual page 44

Table 3.1(continued). System Bus Signal Names
SIGNAL
PIN
A7
A6
A25
A26 A5
A27 A4
A28 A3
A29 A2
A30 Al
A31 AO
Bl GND
RESET
B2
+5 VDC
B3
B4
IRQ2
— 5 VDC
B5
B6 DRQ2
— 12 VDC
B7
N.C.
B8
B9 +12 VDC
BIO GND
MEMW+
Bll
MEMR+
B12
B13 IOW*
B14 IOR*
B15 DACK3+
B16
DRQ3
B17 DACKI*
B18 DRQI
DEFINITION
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit I
Address bit 0
Ground
When high, resets or initializes system logic devices.
+ 5 VDC bus.
Interrupt request 2.
Not used.
Available for assignment to a user-selected device.
— 5 VDC bus.
DMA request 2.
Assigned to floppy disk controller.
— 12 VDC bus.
No connection.
+12 VDC bus.
Ground
Memory write.
When low, causes data on data bus to be stored
in memory.
Memory read.
When low, causes memory to drive data onto the
data bus.
I/O write.
When low, instructs an I/O device to read the
data on the data bus.
I/O read.
When low, instructs an VO device to drive its data
onto the data bus.
DMA acknowledge 3.
Assigned to the Winchester drive controller.
DMA request 3.
Assigned to the Winchester drive controller.
DMA acknowledge 1.
Not used.
Available for user assignment.
DMA request 1.
Page 3.5
System Input/Output