System Bus Signal Names - Zenith Z-100 Reference Manual

page 3.4
System Input/Output
Connection to the bus by the cards in the system is also made through the edge
connectors on the backplane board. Each of the standard cards, and any custom
add-on cards, interface with the CPU through one of these connectors.
This chapter will be limited to defining the signals which appear on the electrically
parallel pins of these connectors. Details on the remainder of the system can
be found in the individual chapters which relate to a given function.
Table 3.1 defines the I/O bus signals.
Table 3.1. System Bus Signal Names
P IN SIG N A L
I/O CHCK
4
Al
A2 D7
A3 D6
A4 D5
D4
A5
D3
A6
A7 D2
A8 Dl
A9 DO
AIO I/O CHRDY
All AEN
A12 A19
A13 A1 8
A14 A1 7
A15 A1 6
A16 A1 5
A17 A1 4
A18 A1 3
A19 A1 2
A20 Al l
A21 A10
A22 A9
A23 A8
DEFINITION
VO channel check
Provides the CPU with parity error status for
memory or other I/O devices.
Active low indicates error.
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit I
Data bit 0
VO channel ready.
Used by slower I/O devices to ensure data is not
lost during read and write operations.
May be held low (not ready) up to 10 CLK cydes
(210 ns).
Address enable.
Assigns control of read and write operations to
the DMA controller.
Address bit 19
Address bit 18
Address bit 17
Address bit 16
Address bit 15
Address bit 14
Address bit 13
Address bit 12
Address bit 11
Address bit 10
Address bit 9
Address bit 8
CI