Memory Access Operations - Zenith Z-100 Reference Manual

Page 6.6
System Memory

Memory Access Operations

A memory access cyde may be initiated by one of three requests: memory read,
memory write, or refresh. The Address Enable Signal (AEN) must also be active
for any of these requests to initiate access.
Contention between these requests, timing, and row and column address selection,
is handled by the address logic. This circuitry also determines which memory
card is being addre'ssed if more than one card resides in the system.
The memory banks consist of nine 6665 or 4164 dynamic RAM ICs per bank
A total of five banks may reside on each of two memory cards. Each bit-addressable
IC can hold 64K by 1 bit, for a total of 64 kilobytes per bank, plus one parity
bit per byte.
Refresh is handled on-chip and is automatically initiated whenever a location is
read. During an actual refresh cycle, all rows in all banks are read simultaneously,
automatically refreshing them.
The parity RAMs are also 6665 or 4164 ICs. One of these chips in each bank
supplies storage space for one additional bit which is used to check parity. The
system is configured for odd parity.
Address Multiplexing and Buffering
The address multiplexers provide the means to address all the memory using
only eight address bits (nine, if 256 kilobit chips are used) and to buffer the
system bus from the memory bus.
When a row is being addressed, AO through A7 and A16 are present on the
multiplex bus as MAO through MAS. During a column address, A8 through A15
and A17 are present as MAO through MAS. The row address signal on these
devices toggles between a logical 1 and a logical 0 to place one group of bits
or the other on the multiplex bus.
The memory banks first latch off the low order group of bits, then the high order
group, and combine them to form an 18-bit address word.