System Control Block Diagram - Sony DVP-F21 Service Manual

DVP-F21

3-4. SYSTEM CONTROL BLOCK DIAGRAM

MD-91 BOARD
(SEE PAGE 4-39)
CN402 CN401
M001
1 1
M
ROLLER
2 2
MOTOR
3
MD-90 BOARD
(SEE PAGE 4-39)
S203
CON 1
S202 5
CRE
S301
LEV
4
S201
2
COF
MB-99 BOARD(3/4)
(SEE PAGE 4-11,12)
HA 0-21
HD 0-15
(SEE PAGE 3-5,6)
CKM
(SEE PAGE 3-3)
MD-89 BOARD
(SEE PAGE 4-33)
CN104 CN101 CN402
1 12 12
2 13 13 SIGNAL PROCESSOR
(SEE PAGE 3-5,6)
CN102
R0SW1
3 8 8
S102 R0SW2
11 11
REJ
RF/SEFVO
(SEE PAGE 3-4)
XDRVMUTE
CKSW3
5 4 4
CKSW1
1 1 1
S103
R0SW3
RSI 10 10
R0SW4
S104 9 9
RLO
LVSW1
2 2 2
CKSW1
4 3 3
CN104
INS 16
INTERFACE CONTROL
DISC 18
SIGNAL PROCESSOR
(SEE PAGE 3-5,6)
512FSAVD
3-7
IC107
or
FLASH
HA 0-21
HA 0-15
1 5 102 109 111
HA 0-21
XRD 70 XRD
XWRH 71 XWRH
XARPRST 36 XARPRST
XARPIT 17 INT1
XARPCS 62 CS4X
XWAIT 67 XWAIT
XRST 35 XRST
21 ROSW1
22 ROSW2
XRST
XSDPIT 18 INT2
XSDPCS 63 CS5X
48 XDRVMUTE
XLDON 41 XLDON
56 CKSW3
57 CKSW1
33 ROSW3
40 ROSW4
42 LVSW1
78 CKSW2
WP 7 7 WP
IC101
SCL 6 39 SCL
EEPROM
SDA 5 38 SDA
XAVDIT 16 INTO
DREQ0 46 DREQ0
DACK0 47 DACK0
DREQ1 49 DREQ1
DACK1 50 DACK1
XAVDCS2 60 CS2X
XAVDCS3 61 CS3X
81
TRST
IC102 IC102
13 15
14 FSEL
3.5Vp-p (33.6MHz) 3.5Vp-p (33.6MHz)
33MARO 15 33-1OUT
33MAVD 13 33-2OUT
27MAVD 3 27-1OUT
IC102 3
4.2Vp-p (27MHz)
IC108
OTP
118 120 85 100 58
HD 0-15
IC103 54
X1 53
X101
16.5MHz
X0 54 1.0Vp-p (16.5MHz)
WIDE
WIDE 82 WIDE
SI0
SI0 25
SO0
IC103 SO0 26
SC0
SYSTEM SCO 27
XIFCS
CONTROL
XIFCS 51
IFBSY
INT4 20
TRST
XFRRST 76
MAMUTE 83 MAMUTE
VESCS 80 X39CS/XVESCS
SI1 28 SI1
SO1 29 SO1
SC1 30 SC1
XDACS 79 XDACS
XRST
IC102 7
IC102
PLL
XT1 7
X102
27MHz 0.9Vp-p (27MHz)
XT0 8
512FS2CH
512-2OUT 9 512FS6CH
IC102 IC102
10 9
512-1OUT 10
4.3Vp-p (24.6MHz) 4.4Vp-p (24.6MHz)
3-8
VIDEO
(SEE PAGE 3-9,10)
CN104
5 SI0
6 SO0
7 SC0
INTERFACE
4 XIFCS CONTROL
3 XIFBUSY
2 XFRRST
AUDIO
(SEE PAGE 3-9,10)