System Control Block Diagram - Sony DVP-CX875P Service Manual

DVP-CX875P

3-4. SYSTEM CONTROL BLOCK DIAGRAM

MB-107 BOARD (3/6)
(SEE PAGE 4-21, 23)
HA 0 – 21 HA 0 – 21
HD 0 – 15 HD 0 – 15
SIGNAL PROCESSOR
(SEE PAGE 3-5)
XRD
XWRH
XARPIT
XARPCS
XWAIT
XRST
HA 0 – 4, 19 HA 0 – 4, 19
HD 8 – 15 HD 8 – 15
NAND FLASH/
300 CHG MECHA
XRD
CONROL
XWRH
(SEE PAGE 3-13)
XRST
XFRRST
XRST
XSDPIT
RF/SERVO
XSDPCS
(SEE PAGE 3-4)
XDRVMUTE
XLDON
XAVDIT
DREQ0
DACK0
DREQ1
DACK1
XAVDCS2
XAVDCS3
XFRRST
SIGNAL PROCESSOR
(SEE PAGE 3-5)
33MARP
27MAVD
512FSAVD
05
IC106 IC107
or
32M FLASH OTP
1 – 5 102 – 109 111 – 118 120 85 – 100
HA 0 – 21 HD 0 – 15
IC104 tf
17 INT1
62 CS4X
67 XWAIT
1.7 Vp-p (16.5 MHz)
35 XRST
IC104
SYSTEM
CONTROL
18 INT2
63 CS5X
48 XDRVMUTE
82 XLDON
16 INTO
46 DREQ0
47 DACK0
49 DREQ1
50 DACK1
60 CS2X
61 CS3X
81
IC103 8
14 FSEL
XTI
7
1.5 Vp-p (27 MHz)
X102
27MHz
IC103 4
8 XTO
3.5 Vp-p (27 MHz)
3-7
HA 1 – 16
HD 0 – 15
XWRH
58 70 71 72 XRD
XSRWE
84
CS1X 59
X1
53
X101
16.5MHz
X2 54
SDA 38 5 SDA
IC101
SCL 39 6 SCL
EEPROM
WP 7 7 WP
AN3 15
WIDE 36
SI0 25
SO0 26
SCO 27
XIFCS 51
INT4 20
XFRRST 76
INT3 19
CS6X 65
CPUCK 77
MA_MUTE 83
SO1 29
SC1 30
XDACS 79
512-2OUT 9
IC103
512-1OUT 10
PLL
27-2OUT 4
33-1OUT 15
IC103 qg
3.2 Vp-p (33.87 MHz)
1 – 5 18 – 21
A 0 – 15
24 – 27 42 – 44
7 – 10 13 – 16
29 – 32 35 – 38 I/O 0 – 15
39 LB
IC108
40 UB
41 OE 1M SRAM
17 WE
6 CS
IPSW
VIDEO
(SEE PAGE 3-10)
WIDE
SCL
VIDEO
SDA
(SEE PAGE 3-9)
XRST
CN103
(1/2)
SI0
SO0
SC0
XIFCS
IFBSY
XFRRST
NAND FLASH/
XGAIT
300 CHG MECHA
XGACS
CONROL
CPUCK
(SEE PAGE 3-13)
MA_MUTE
SO1
SC1
XDACS
AUDIO
(SEE PAGE 3-11)
XRST
512FS2CH
IC103 9, 0
DVD: 3.3 Vp-p (24.57 MHz)
CD: 3.3 Vp-p (22.58 MHz)
3-8
5 SI0
SO0
6
INTERFACE
SC0
7
CONTROL
4 XIFCS
(SEE PAGE 3-15)
3 IFBSY
2 XFRRST