HP 3478A Technical Manual page 103

3478A
Function
and Range
ACV 300mV
ACV 3 V
ACV 30 V
ACV 300 V
ACI 300mA
ACI 3 A
range and function selected). The gains are determined
by resistors RA5, RA6, RA7, and RA8 (all in U102), as
shown in Figure 7-F-5. The gain determining resistors
are selected by FETs S7AC to SIOAC (all in U102) which
operate as switches (see Table 7-F-2). Resistor RA9 (in
U102) is used for the amplifier to have the same high
frequency response in X4 gain as in X.4 gain. Resistors
R306 and R307, and C310 and C312 are used to filter
the + 15V and -15V power supplies, respective- ly.
c. The third amplifier stage (U302) is a non-
inverting amplifier with a gain of X25 in all ac ranges and
func- tions. The output of the amplifier is applied to the
RMS Converter and is 3V RMS for all full scale ac inputs
in all ac functions and ranges. Capacitor C305 is used
for high frequency compensation (for flat gains at high
fre- quency).
7-F-29. True RMS Converter (U303). The True RMS
Converter's output is a positive dc voltage with its value
equal to the true rms value of the input. For example, a
sine wave input of IV RMS ac generates a + 1V dc out-
put.
7-F-30. Refer to Schematic 2. The RMS Converter has
one major stage that does the actual conversion and a
buffer (used as an output stage). The converter stage
and the buffer are externally connected by R304. Pin 9
of U303 is the input to the buffer and pin 10 is the out-
put of the converter stage. The gain of the buffer is X1
which is internally set. Capacitor C307 is the RMS Con-
verter's averaging capacitor and C308, C309, and
resistor R304 are used with the buffer as a ripple filter.
7-F-31. A/D Converter
7-F-32. General. The A/D Converter is used to change
dc voltages to digital information. The circuitry consists
of an Integrator (U401 and associated circuitry), Voltage
Reference (U461 and associated circuitry), and the A/D
Hybrid (U403). The A/D Converter operation is
controlled by the A/D Controller (U462).
7-F-33. The A/D conversion method used by the 3478A
is called Multi-Slope II and has two operating states:
Runup and Rundown.
digits are determined during runup (see paragraph 7-F-
41) and the least significant digits are determined during
rundown. The integration time depends on the
Table 7-F-2. AC Amplifier Gains
Stag 1
Gain
.1
.1
.001
.001
1
1
The 3478A's most significant
Stag 2 Total
Gain Gain
4 10
.4 1
4 .1
.4 .01
4 100
.4 10
selected Number Of Digits Displayed (3 1/2, 4 1/2, or 5
1/2). To help understand Multi-Slope II, first consider the
operation of the Dual-Slope Conversion method. This
method is explained in the following paragraph.
7-F-34. Dual-Slope Conversion. In dual-slope conver-
sion, an integrator capacitor charges for a fixed time
period (as shown in Figure 7-F-6), which is done during
runup. The charging rate and the resultant amplitude of
the charge is proportional to the voltage applied to the
integrator. The integrator capacitor is then discharged at
a fixed rate determined by a known reference voltage
and is done during rundown. Since the discharge rate is
constant, the discharge time is proportional to the
amplitude of the charge (input voltage). The amplitude
level can then be determined by the discharge time. 7-F-
35. Multi-Slope II Conversion. Multi-Slope II is similar to
Dual-Slope in that a capacitor is charged and discharged
by the input voltage and by known reference voltages.
The following paragraphs explain the Multi- Slope II
operation (runup and rundown).
7-F-36. Simplified Explanation of Runup. The Runup
operation lasts for 349 A/D counts with one A/D count
equal to 30 (36 in the 50Hz option) cycles of the ALE
clock (Address Latch Enable at U462 pin 11). Each A/D
count results in one A/D ramp (or slope) at the output of
the A/D Integrator. The same time is used in both the 5
1/2 and 4 1/2 digit mode (349 ramps), with 10 readings
taken in the 5 1/2 digit mode (making the integration time
time longer, see paragraph 7-F-40). Only 34 ramps are
used in the 3 1/2 digit mode.
generated.by the A/D Controller (U462, also known as
the Floating Common CPU). Refer to Figure
Figure 7-F-6. Dual Slope Conversion
7-F-9
TM 11-6625-3071-14
Switches (FETs)
Enabled
S2AC,S4AC,S5AC,S8AC,S10AC
S2AC,S4AC,S5AC,S7AC,S9AC
S1AC,S3AC,S6AC,SBAC,S10AC
S1AC,S3AC,S6AC,S7AC,S9AC
S4AC,S5AC,S8AC,S10AC,S1 1AC
S4AC,S5AC,S7AC,S9AC,S1 1AC
The ALE clock is