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XOR Start Signal
1
Pin A is assigned to the output direction, and pins 1 through 6 are assigned to the input direction. It can be seen that after
all pins 1 to 6 are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin A.
The following is the truth table for the XOR tree shown in
Table 7-2 Example of an XOR Tree
Test Vector
Input Pin 1
number
1
2
3
4
5
6
7
7.3.2
Description of the RX881 XOR Tree
7.3.3
XOR Tree Activation
The RX881 chip enters the XOR tree test mode by means of the JTAG. First, the 8-bit instruction register of the JTAG is
loaded with the XOR instruction ("00001000"). This instruction assigns the input direction to all the pins except pin TDO,
which is assigned the output direction to serve as the output of the XOR tree. After loading, the JTAG is taken to the
Run-Test state for completion of the XOR tree initialization.
A 10MHz clock frequency for the Test Mode Clock (I2C_CLK) is recommended for the XOR TREE test mode. A pair of
differential clock at 10MHz should also be supplied to HT_REFCLKP/N to enable I/Os for testing.
7.3.4
XOR Tree for the RX881
The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the
TDO Pin. Refer to
tree will cause the output to toggle.
There is no specific connection order to the signals on the tree. When the XOR tree is activated, any pin on the XOR tree
must be either pulled down or pulled up to the I/O voltage of the pin. Only pins that are not on the XOR tree can be left
floating.
When differential signal pairs are listed as single entries on the XOR tree, opposite input values should be applied to the
two signals in each pair (e.g., for entry no. 1 on the tree, when "1" is applied to HT_RXCAD0P, "0" should be applied to
HT_RXCAD0N).
46136 AMD RX881 Databook 1.40
7-2
2
3
Figure 7-1 Example of a Generic XOR Tree
Input Pin 2
0
0
1
0
1
1
1
1
1
1
1
1
1
1
Table 7-3
for the list of the signals included on the XOR tree. A toggle of any of these balls in the XOR
4
5
Figure 7-1
The XOR start signal is assumed to be logic 1.
Input Pin 3
Input Pin 4
0
0
0
0
0
0
1
0
1
1
1
1
1
1
6
Input Pin 5
Input Pin 6
0
0
0
0
0
0
0
0
0
0
1
0
1
1
© 2011 Advanced Micro Devices, Inc.
XOR Test
A
Output Pin A
1
0
1
0
1
0
1
Proprietary
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