Test Capability Features; Test Interface; Xor Test; Description Of A Generic Xor Tree - AMD RX881 Data Book

7.1

Test Capability Features

The RX881 has integrated test modes and capabilities. These test features cover both the ASIC and board level testing.
The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part. The board level
tests modes can be used for motherboard manufacturing and debug purposes. The following are the test modes of the
RX881:
•
Full scan implementation on the digital core logic that provides about 99% fault coverage through ATPG (Automatic
Test Pattern Generation Vectors).
•
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
•
Improved access to the analog modules and PLLs in the RX881 to allow full evaluation and characterization of these
modules.
•
A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) to allow board level testing of
neighboring devices.
•
An XOR TREE test mode on all the digital I/O's to allow for proper soldering verification at the board level.
•
A VOH/VOL test mode on all digital I/O's to allow for proper verification of output high and output low voltages at
the board level.
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
7.2

Test Interface

Table 7-1
Pins on the Test Interface
Pin Name
TESTMODE
NC
NC
NC
NC
POWERGOOD
7.3

XOR Test

7.3.1

Description of a Generic XOR Tree

An example of a generic XOR tree is shown in the
© 2011 Advanced Micro Devices, Inc.
Proprietary
Ball number Type
D13 I
B8 I
A9 I
B9 I
D9 O
A10 I
Description
IEEE 1149.1 test port reset
TMS: Test Mode Select (IEEE 1149.1 test mode select)
TDI: Test Mode Data In (IEEE 1149.1 data in)
TCLK: Test Mode Clock (IEEE 1149.1 clock)
TDO: Test Mode Data Out (IEEE 1149.1 data out)
I/O Reset
Figure 7-1
.
Chapter 7
Testability
46136 AMD RX881 Databook 1.40
7-1