Yamaha RX-Z11 Service Manual page 176

A B C
RX-Z11/DSP-Z11
DVIDEO 1/4
1
DVIDEO (1)
CB601
0
5.0
0
0
5.0
0
5.0
0.1
5.0
3.3
0.1
0
2
0
12.0
3.3
12.0
3.3
0.1
0
0
3.1
0.1
0
0.1
0
0.1
3.3
0.1
3.3
0.1
3.2
Page 161 H3
0.1
3.3
to DSP_CB781 0.1
3.3
0.1
3.2
0
3
3.2
0.1
3.2
0.1
0
0.1
3.2
0.1
3.2
0.1
3.2
0.1
3.3
0.1
3.2
0.1
3.2
0
3.2
0.1
3.2
0.1
0
0.1
3.2
0.1
4
3.3
0.1
3.3
0.1
3.3
0.1
3.3
3.3
0
0
5.0
0
5.0
5.0
5.0
5.0
3.3
0.1
3.3
5.0
3.3
5.0
3.3
0
0
5
6
3.3 3.3
3.3 IC652
0.1
IC651 3.3 3.3
3.3
0 0
IC651 IC652
IC652
3.3
0
0.1
3.3
3.3
3.3
3.3
3.3
0
7
3.3
3.3
3.3
0
1.8
0
3.3
3.3
3.3
0
3.3
3.3
3.3
0
3.3
3.3
3.3
3.3
3.3
3.3
0
3.3
0
0
0
5.0
0
8
3.3
IC656
0
0
0.1
0 IC656
9
0 5.0
0.1 0
0 0
3.3 0
3.3
5.0
0 3.3
5.0 0
5.0 3.3
0 3.3
0
0
IC655
5.0
0.1 IC654
5.0
3.3
10 IC654
0 IC654
0.1
0 0
IC654
176
D E F
0
0
0
1.7
0
IC848
3.3
0
0.1 0.1
0
0.1 0
0
0.1 0
0
0.1 0 0
0.1 0.5
0
0.1 0 0
0.1 0.5
0
0.1 0.8
0
0 0.5
6.2
IC849
3.3 0
6.2
0.1 0.1
0 0
0.1
6.2
0.1 0
0.1 0 0
6.2
0.1 0
0 1.7
0.1
6.2
0.1 0
0
0.1 0
6.2
0 0
1.7
IC850
3.3 1.8
0 0
0.1
0.1 0
0.1 0.8 1.7
0.1 0 4.2
0.1 0
0
0.1 0 4.2
0.1 0
0
0.1 0 4.2
0 0 5.0
4.2
0
4.2
3.3
4.2
3.3
0
0
0
IC851 5.0
3.3
0
3.2 0.1
5.0
3.2 3.2
0
3.2 3.2
3.3
3.3 3.2
0
3.3 3.0
3.3
3.2 3.2
0
3.3 3.2
3.3
3.3 3.2
0
0 3.2
0
IC852
3.3 0
3.2 0.1 0.1
3.2 3.1 0
3.2 3.2 3.3
3.2 3.2 0
3.3 3.2 3.3
3.2 3.1 0
3.2 3.2 3.3
3.2 3.2 0
0 3.2 5.0
0
IC853
3.3 5.0
3.3 0.1
0
0
3.3 5.0
3.3 3.2
0
3.3 3.3 0
3.3 3.3
0
0
3.3 3.3
0 3.3
0
3.3
3.3 0
0 0
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
3.3 4.2 0
3.3
4.2
3.3
0
0 0
4.2
3.3
0.1
0.1
VIDEO
0.1
0.1
0
0
MICROPROCESSOR
3.3
(NPGA 2) 0
0
3.3
0
0
0
3.3
IC653 0
0
3.1
0
0
3.3
0
0
0
3.3
0
0
3.3
G H
CB604
1.3
CB801 0
0
0
0
0
Page 173 H2 0
0
0
to AVIDEO (1)_CB101 0.1
0
0.1
0
0.1
Page 161 N3
to DSP_CB782
POINT C-1 XL803 (Pin 80 of IC801)
0.7
0
0.7
0
0.4
0
Page 173 I2 0.4
0
0.7
to AVIDEO (1)_CB102 0
0.4
0
3.3
CB802
CB803 3.3
3.3
5.0
0
5.0
5.0
3.3
5.0
Page 173 J2 0.1
3.3
3.3
to AVIDEO (1)_CB103 3.3
5.0
3.3
3.3
0
0.1
5.0
0
IC601: R1172S331B-E2-F
CMOS-based positive-voltage regulator IC
V DD 6
CB622
6.2
2.8
Page 175 C2
2.7
4.2
to AVIDEO (3)_W702 Vref
4.2
0
Current Limit
CE 3
CB623
0 Page 169 F5
0
0
to POWER (3)_W552
Pin No. Symbol
1 V Output Pin of Voltage Regulator
0 OUT
2, 5 GND Ground Pin
0
3 CE Chip Enable Pin
0
4 NC No Connection
6 V Input Pin
DD
CB627
-35.3
5.0
1.4
1.8
Page 169 F6
5.0
IC848-853: SN74CBTLV3245APWR
0
5.0 to POWER (3)_W702
Low voltage octal FET bus switch
0
12.1
0
0 NC 1 20 V
CC 2
A1
A1 2 19 OE
CB628 A2 3 18 B1
1.4
A3 4 17 B2
1.8 9
Page 169 J7 A4 5 16 B3 A8
5.0
0.9 A5 6 15 B4
0 to POWER (2)_W554 A6 7 14 B5
19
0 OE
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
CB815
0
0
5.0
5.0
5.0
5.0
5.0
5.0
0
3.3
0.1
5.0 Page 171 E2
0
1.8
to SUBCPU (1)_CB782
1.4
0
5.0
0
5.0
5.0
5.0
0.9
5.0
IC655: TC74VHCT245AFT
5.0 IC651: TC7SH04FU-TE85L
0
Inverter Octal bus transceiver
NC 1 5 VCC
A Y
IN A 2
CB629
3.3 L H
5.0 GND 3 4 OUT Y H L
3.3
0
3.3
3.3
3.3
IC652: TC7SH32FU
3.3
3.3
2-input OR gate
3.3
3.3
Page 172 M2
0
0
IN B 1 5
0 to SUBCPU (6)_CB992 V CC
A B Y
0 H H H
IN A 2
3.3
L H H
0 GND OUT Y H L H
3 4
0 L L L
5.0
0
5.0
IC654: TC7WT125FU
5.0
5.0
Dual bus buffer
3.3
0
5.0
-35.3 G1 1 8 Vcc
A1 2 7 G2
Y2 3 6 Y1
GND 4 5 A2
I J K
0 2.4
0 2.4
0.5 2.3
0.1
2.5
0
C-1 1.8
1.2
2.5
0 0
0.5 2.5
0 1.8
0.5 0
0 2.4
0
0.1
3.3 2.4
1.6 2.4
2.0 2.4
0 2.4
IC801
3.3 2.4
0.9 2.4
1.8 2.5
1.1 2.5
0.6 2.5
0.5 1.8
0 0
1.7 2.5
0
2.6
0.5 3.1
0 3.1
1.6
0 0
0 3.3
0
0
A/D DECODER
3.3 0.1
3.3 0.1
0.1
0
0 0.1
0 0.1
0
0
0 0.1
0 0.1
0 0.1
0 0.1
1.0 0.1
1.8
2.0
0.2
0.4 0.3
0.7 0
0.4 1.8
IC802
0 0.4
3.3 3.0
0.7 0.9
0.7
1.0
0.4 1.0
2.4 1.0
0.1 0
0.3 0
3.1
IC801: ADV7802BSTZ-150
12-bit, SDTV/HDTV 3D comb filter, video decoder and graphics digitizer
DDR/SDR-SDRAM INTERFACE
STANDARD DEFINITION PROCESSOR (SDP)
1 V OUT
12 12 12
ANTIALIAS
CLAMP ADC DDR/SDR-SDRAM INTERFACE
FILTER
AIN1
TO
12 12
AIN12 ANTIALIAS 525p/625p MACROVISION STANDARD
CLAMP ADC
FILTER SUPPORT DETECTION AUTODECTION
CVBS
S-VIDEO
12 12
YPrPb ANTIALIAS
SCART- CLAMP ADC AV CODE
FILTER 2D COMB VERTICAL
(CBVS+RGB) INSERTION
GRAPHICS RGB PEAKING
2,5 GND
12 12
CLAMP ANTIALIAS
ADC
FILTER COLORSPACE
HORIZONTAL CONVERSION
FAST BLANK
3D COMB PEAKING
OVETLAY
CONTROL
Description FB
CTI
TBC
LTI
11
CVBS OUT DAC
24
P30 TO P53
HS_IN2 CORE
DIGITAL INPUT PORT
VS_IN2 CLK VBI DATA PROCESSOR (VDP)
CLK_IN DVI OR HDMI COMPONENT PROCESSOR (CP)
DE_IN
MACROVISION ACTIVE PEAK
HS_IN SYNC PROCESSING AND
DETECTION AND AGC
CLOCK GENERATION
VS_IN
SOG
DIGITAL
SSPD STDI COLORSPACE
SOY GAIN OFFSET
FINE
CONVERSION CONTROL CONTROL
18 CLAMP
SW B1
SCLK
SCLK2
SERIAL INTERFACE
SDA
CONTROL AND VBI DATA
11 SDA2
SW B8
ALSB
IC803: MT46V8M16P-6T
IC804: LP2995MX
Double Data Rate (DDR) SDRAM
DDR termination regulator
AV V PV
IN DDQ IN
6 5 7
CKE
CK#
50k
CK
V 4 8 CS# CONTROL
REF V TT
LOGIC
50k
WE#
3 V SENSE
CAS#
RAS# REFRESH
COUNTER
12
2
GND
MODE REGISTER
ROW-
ADDRESS
MUX
14
12
IC845-847: SN74LVC245APWR
Octal bus transceivers with 3-state outputs
2
DIR 1 20 Vcc
DIR Vcc
1 20 A0-A11,
ADDRESS
BA0, BA1 14
A1 2 19 OE REGISTER
A1 2 19 G 2
A2 3 18 B1
A2 3 18 B1
A3 4 17 B2
A3 4 17 B2
A4 5 16 B3
A4 5 16 B3
A5 6 15 B4
9
A6 B5
7 14 A5 6 15 B4
A7 8 13 B6
A6 7 14 B5
A8 9 12 B7
A7 8 13 B6
GND 10 11 B8
A8 9 12 B7
GND 10 11 B8
IC656: TC7SH125FU
Bus buffer
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
G 1 5 V
CC with parts having specifications equal to those originally installed.
IN A 2 # Schematic diagram is subject to change without notice.
GND 3 4 OUT Y
L M N
IC803
0 2.5
0 2.5
2.5 2.5
IC804
0.5 2.5 1.3
0.8 2.5 0
2.5
0.7 2.5
1.3 2.5
2.0 2.5
1.3 2.5
0.6 2.5
0.5
0.6
0.7 0
0.8 0
1.2 0
0 0
0 0
0 0
0
0 0
0
2.5 1.3
2.5
2.4 1.8
2.4 2.5
2.4 0
2.3 2.5
2.5
2.5 2.5
1.3 2.5
1.4 2.4
2.4
2.4
2.4
2.4
2.4
0.1
2.4
IC845 IC846 IC847
0
0
3.3
ENCODER D/A
IC802: ADV7342BSTZ
Multiformat video encoder
SCL/ SDA/ ALSB/ SFL/
DGND (2) V DD (2) MOSI SCLK SPI_SS MISO AGND V AA
ADV7342/ADV7343
GND_IO VBI DATA SERVICE SUBCARRIER FREQUENCY
INSERTION MPU PORT LOCK (SFL)
VDD_IO
11-BIT
DAC 1
54 YUV
PIXEL DATA 16x
PROGRAMMABLE TO
P0TO P53 ADD FILTER
10-BIT LUMINANCE YCrCb/ 11-BIT
RGB/YCrCb SYNC FILTER
SD 4:2:2 TO 4:4:4 RGB DAC 2
TO
HD DDR YUV
VIDEO DEINTERLEAVE MATRIX ADD PROGRAMMABLE 16x 11-BIT
SIN/COS DDS
BURST CHROMINANCE FILTER DAC 3
DATA BLOCK
FILTER
CS/HS
R 11-BIT
RGB
RGB DAC 4
ASYNC
BYPASS
VS G/B
11-BIT
YCbCr YCbCr DAC 5
20-BIT PROGRAMMABLE
TO
FIELD/DE ED/HD HDTV FILTERS
ITOP ED/HD INPUT RGB MATRIX 4x
HDTV FILTER
SHARPNESS AND 11-BIT
TEST
DEINTERLEAVE ADAPTIVE FILTER DAC 6
VIDEO PATTERN
CONTROL
DATA GENERATOR
SFL/SYNC_OUT
POWER REFERENCE
16x/4x OVERSAMPLING
MANAGEMENT VIDEO TIMING GENERATOR AND CABLE
DAC PLL
CONTROL DETECT
LLC
P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC CLKIN (2) PV DD PGND EXT_LF (2) V REF COMP (2)
INT
AV CODE
INSERTION
V DD 1 66 V
BANK3
DQ0 2 65 DQ15
BANK2
V DD Q 3 64 V
BANK1
DQ1 4 63 DQ14
DQ2 5 DQ13
62
V SS Q 6 61 V
DQ3 7 60 DQ12
DQ4 8 59 DQ11
V DD Q 9 58 V
DQ5 10 DQ10
12 BANK0 57
CK
ROW- BANK0 DQ6 11 56 DQ9
ADDRESS MEMORY V SS Q 12 55 V
4096
LATCH ARRAY DQ7 13 54 DQ8
& (4,096 x 256 x 32) DATA DLL NC 14 53 NC
DECODER
16 V Q 15 52 V
DD
32 16 LDQS 16 51 UDQS
READ MUX
SENSE AMPLIFIERS NC 17 50 DNU
LATCH 16 DRVRS
V DD 18 49 V
8192 DQS 2 DNU 19 48 V
GENERATOR LDM 20 47 UDM
DQ0-DQ15 WE# 21 CK#
46
COL0 CAS#
DQS 22 45 CK
INPUT
I/O GATING RAS# 23 44 CKE
32 REGISTERS LDQS
BANK DM MASK LOGIC CS# 24 43 NC
2 2 UDQS
CONTROL NC 25 42 NC
MASK
LOGIC 2 BA0 26
41 A11
WRITE 2 2
256 4 BA1 27 40 A9
32 FIFO
(x32) A10/AP 28 39 A8
& 16 16 RCVRS LDM,
DRIVERS A0 29 38 A7
32 UDM
16 30 37 A6
A1
COLUMN CK CK 16 16 31 A5
A2 36
DECODER Out In DATA
A3 32 35 A4
COLUMN- V DD 33 34 V
ADDRESS 8
CK
COUNTER/ 2
LATCH
COL0
1
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
R SET (2)
SS
SS Q
DD Q
SS Q
DD Q
Q
SS
REF
SS
SS