Yamaha RX-Z11 Service Manual page 100

RX-Z11/DSP-Z11
No. Port Name
46 VDD
47 SI2
48 TXD0
49 RXD0
50 PI4_XCTS0
51 PO4_XRTS0
52 PIO[25]
53 PIO[26]
54 VDD
55 VSS
56 PIO[27]
57 TXD1
58 RXD1
59 PI5_XCTS1
60 PO5_XRTS1
61 PIO[9]
62 PIO[10]
63 PIO[11]
64 PIO[12]
65 VDD
66 VSS
67 PIO[13]
68 PIO[14]
69 TXD2
70 RXD2
71 PI6_XCTS2
72 PO6_XRTS2
73 VDD
74 VSS
75 VCXI0
76 VDD
77 PI2_X0IN
78 NC
79 VCXO0
80 PI3_X1IN
81 VSS
82 VDD
83 VCXI1
84 VSS
85 XIC
86 NC
87 VCXO1
88 TEST0
89 CLKIN
90 VDD
91 VSS
92 TEST1
93 TEST2
94 PO1_XLOCK
95 XPCO
96 PCO
97 PO2
98 PO3
99 PO0_MCLKO
100 AMCKO
101 VDD
102 VSS
103 AHCKI
104 A[7]
105 A[6]
100
Function Name
I/O [OFF]
(P.C.B.)
MCU
NC SI
XM_MOSI SO
XM_MISO SI
TUN_N_TUND I
FL_N_RST O
SPI_RDY3 I
SPI_RDY4 I
MCU
MCU
SPD_ZSEL0 O
– SO
– SI
TUN_N_ST I
– O
OPT_N_INH O
PCM_DSD_SEL O
OSD_N_CS O
VEX_N_CS O
MCU
MCU
AEX_N_CS O
VEX_N_RST O
HDRD_MOSI SO
HDRD_MISO SI
IPCP_READY I
OSD_N_RST O
MCU
MCU
PLL
MCU
EXT_22M PLL
MCU
PLL
EXT_24M MCU
MCU
MCU
PLL
MCU
DEV_N_RST MCU
MCU
PLL
TEST0 MCU
DIR_24M_1 MCU
MCU
MCU
TEST1 MCU
TEST2 MCU
PLL_N_LOCK O
N_PCO PLL
PCO PLL
EX22M_OFF O
EX24M_OFF O
GA_MCKO PLL
GA_AMCKO PLL
MCU
MCU
45.1584MHz PLL
SA[7] BUS
SA[6] BUS
Detail of Function
XM Radio asynchronous serial data transmission
XM Radio asynchronous serial data reception
TUNER TUNED input
Reset for FL driver
SDP Serial Ready #2
DSP Serial Ready #3
SPDIF coaxial OUT selector control
UART Reserve
UART Reserve
TUNER STEREO detect input
Optical REC OUT output inhibit control / Low: output inhibit
NPGA LRCKI input select: 0=I2S, 1=DSD
OSD chip select
Video expansion port (LC709004A) chip select
Audio expansion port (LC709004A) chip select
Video expansion port (LC709004A) reset
HD Radio asynchronous serial data transmission
HD Radio asynchronous serial data reception
iPod certification chip READY input (Reserve)
OSD reset output
Oscillation circuit for PLL
External VCX0 clock input for PLL (not used for TP)
Oscillation circuit for PLL
External VCX0 clock input for PLL (not used for TP)
Oscillation circuit for PLL
Reset input
Oscillation circuit for PLL
For TEST
System clock input
For TEST
For TEST
PLL clock detect output
PLL phase comparator output
PLL phase comparator output
22.5792MHz external oscillation circuit ON/OFF control
24.576MHz external oscillation circuit ON/OFF control
Jitter reduction PLL audio master clock output
Master clock (11.2896MHz) output for MC streaming reproduction
45.158MHz clock input for generation of 11.2896MHz
HOST I/F address bus
HOST I/F address bus