Function Name
No.
Port Name
(P.C.B.)
41
SO1
VOL_MOSI
42
SI1
43
SCK2
FPGA_SCK
44
SO2
FPGA_MOSI
45
VSS
46
VDD
47
SI2
FPGA_MISO
48
TXD0
IPD_MOSI
49
RXD0
IPD_MISO
50
PI4_XCTS0
FPGA_CDONE
51
PO4_XRTS0
HRX_N_RST
52
PIO[25]
YGV_N_RST
53
PIO[26]
ABT_N_RST
54
VDD
55
VSS
56
PIO[27]
VIPC_N_RST
57
TXD1
58
RXD1
59
PI5_XCTS1
FPGA_N_STA
60
PO5_XRTS1
HTX1_N_RST
61
PIO[9]
FPGA_N_INT
62
PIO[10]
DAC_N_CS
63
PIO[11]
MISEL_N_CS
64
PIO[12]
MVOL_N_CS
65
VDD
66
VSS
67
PIO[13]
ZVOL_N_CS
68
PIO[14]
VDEC_YGV_N_OE
69
TXD2
70
RXD2
71
PI6_XCTS2
HDMI_MUT
72
PO6_XRTS2
HTX2_N_RST
73
VDD
74
VSS
75
VCXI0
76
VDD
77
PI2_X0IN
78
NC
79
VCXO0
80
PI3_X1IN
81
VSS
82
VDD
83
VCXI1
84
VSS
85
XIC
DEV_N_RST
86
NC
87
VCXO1
88
TEST0
TEST0
89
CLKIN
DIR_24M_3
90
VDD
91
VSS
92
TEST1
TEST1
I/O [OFF]
SO
Serial data output for main volume (NJW1195) control
SO
Serial data output for zone volume (NJW1194) control
SO
Serial data output for mix analog switch (NJU7313) control / ES correction
required : 3.3V to 5.0V conversion required
SO
Serial data output for zone channel assign SW (NJW1111) control
–
SI
SO
Serial clock output for FPGA configuration / Control
SO
Serial clock output for IP conversion IC (IP00C772) control
SO
Serial data output for FPGA configuration / control
SO
Serial data output for IP conversion IC (IP00C772) control
MCU
MCU
SI
Serial data input for FPGA configuration / Control
SI
Serial data input for IP conversion IC (IP00C772) control
SO
iPod asynchronous serial data transmission
SI
iPod asynchronous serial data reception
I
CONF_DONE input for FPGA configuration
O
Reset of HDMI Rx only
O
Reset signal to video GUI (YGV619)
O
Reset signal to video scalar
MCU
MCU
O
Reset signal to video IP conversion IC (IPSD1)
–
SO
UART reserve
–
SI
UART reserve
I
nSTATUS input for FPGA configuration
O
Reset of HDMI Tx1 only
IRQ
Interrupt from FPGA (for VSYNC count of HDMI, unused in the current state)
O
DAC chip select
O
Chip select for main input selector (NJU731X) control
O
Main volume/Chip select
MCU
MCU
O
Zone volume/Chip select
SW (NJW1111) for zone channel assign/chip select
O
Video bus from VDEC to YGV enable
–
SO
UART reserve
–
SI
UART reserve
I
HDMI MUTE input
O
Reset of HDMI Tx2 only
MCU
MCU
BUS
MCU
–
BUS
MCU
BUS
–
MCU
MCU
MCU
MCU
MCU
MCU
Reset input
MCU
MCU
MCU
For TEST
MCU
System clock input
MCU
MCU
MCU
For TEST
RX-Z11/DSP-Z11
Detail of Function
103