Dma Configuration Registers - Texas Instruments TMS320VC5509 Data Manual

Fixed-point digital signal processor
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PORT ADDRESS
REGISTER NAME
(WORD)
0x0E00
DMA_GCR[2:0]
0x0E03
DMA_GTCR
0x0C00
DMA_CSDP0
0x0C01
DMA_CCR0[15:0]
0x0C02
DMA_CICR0[5:0]
0x0C03
DMA_CSR0[6:0]
0x0C04
DMA_CSSA_L0
0x0C05
DMA_CSSA_U0
0x0C06
DMA_CDSA_L0
0x0C07
DMA_CDSA_U0
0x0C08
DMA_CEN0
0x0C09
DMA_CFN0
0x0C0A
DMA_CFI0
0x0C0B
DMA_CEI0
0x0C20
DMA_CSDP1
0x0C21
DMA_CCR1[15:0]
0x0C22
DMA_CICR1[5:0]
0x0C23
DMA_CSR1[6:0]
0x0C24
DMA_CSSA_L1
0x0C25
DMA_CSSA_U1
0x0C26
DMA_CDSA_L1
0x0C27
DMA_CDSA_U1
0x0C28
DMA_CEN1
0x0C29
DMA_CFN1
0x0C2A
DMA_CFI1
0x0C2B
DMA_CEI1
0x0C40
DMA_CSDP2
0x0C41
DMA_CCR2[15:0]
0x0C42
DMA_CICR2[5:0]
† Hardware reset; x denotes a "don't care."
April 2001 − Revised January 2008
Table 3−20. DMA Configuration Registers
DESCRIPTION
GLOBAL REGISTER
DMA Global Control Register
DMA Timeout Control Register
CHANNEL #0 REGISTERS
DMA Channel 0 Source Destination
Parameters Register
DMA Channel 0 Control Register
DMA Channel 0 Interrupt Control Register
DMA Channel 0 Status Register
DMA Channel 0 Source Start Address Register
(lower bits)
DMA Channel 0 Source Start Address Register
(upper bits)
DMA Channel 0 Destination Start Address Register
(lower bits)
DMA Channel 0 Destination Start Address Register
(upper bits)
DMA Channel 0 Element Number Register
DMA Channel 0 Frame Number Register
DMA Channel 0 Frame Index Register
DMA Channel 0 Element Index Register
CHANNEL #1 REGISTERS
DMA Channel 1 Source Destination
Parameters Register
DMA Channel 1 Control Register
DMA Channel 1 Interrupt Control Register
DMA Channel 1 Status Register
DMA Channel 1 Source Start Address Register
(lower bits)
DMA Channel 1 Source Start Address Register
(upper bits)
DMA Channel 1 Destination Start Address Register
(lower bits)
DMA Channel 1 Destination Start Address Register
(upper bits)
DMA Channel 1 Element Number Register
DMA Channel 1 Frame Number Register
DMA Channel 1 Frame Index Register
DMA Channel 1 Element Index Register
CHANNEL #2 REGISTERS
DMA Channel 2 Source Destination
Parameters Register
DMA Channel 2 Control Register
DMA Channel 2 Interrupt Control Register
Functional Overview
RESET VALUE †
xxxx xxxx xxxx x000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xx00 0011
SPRS163H
53

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