Printhead Drive Circuit - Epson LG1-1070 Service Manual

2.3.6
Figure 2-24 shows the printhead
expanded to create the image data. The CPU splits up this data three times and transfers this information
to the latch circuit within the STK-6022B. The CPU samples the voltage of the +35 V line via the A/D
convertor (see Section 2.3.3).
The CPU outputs a pulse via the CPU time output port P83. The length of this pulse corresponds to
the voltage of the +35 V line. This pulse becomes the head drive signal. In this way, STK-6022B outputs
head drive signals (signals HD 1 to HD24) that relate to voltage levels through the length of the pulses.
These signals are output to the head for each of the sections of print data that were created by
subdividing the data three times before sending.
By sampling the +35 V line voltage and determining the length of the head drive signal, it is possible
to maintain the energy supplied to the head at a constant level. If the voltage of the +35 V line is HIGH,
the CPU shortens the output pulse. If the voltage of the +35 V line is LOW, the CPU lengthens the output
pulse.
Figure 2-25 shows the timing of-the output of the head drive signal.
CPU (Ic)
DO-7
CPU
drive circuit in block diagram form. The print data already has been
.
E 0 5 A 5 0 (4D)
Figure 2-24. Printhead Drive Circuit
r - - - - - - - - - -
1
1 t
L - - - - - - - - - -
J
Figure 2-25. Head Drive Signal Output Timing
DO-7
HD 1-24
1
L - - - - - -
2 - 1 9
. - - - - J
REV.-A