I/O Address Assignments; Configuration Data Register Bit Assignments; I/O Address Cross-References - Intel NetStructure MPCBL0001 Technical Product Specification

®
Intel NetStructure MPCBL0001 High Performance Single Board Computer
Contents
CONFIG_DATA is a 32-bit read/write window into the PCI configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
Table 55.

Configuration Data Register Bit Assignments

Bit
Configuration Data Window (CDW): If bit 31 of CONFIG_ADDRESS is set to 1, any I/O access to
31:0 the CONFIG_DATA register is mapped to configuration space pointed to by the contents of
CONFIG_ADDRESS.
5.2

I/O Address Assignments

I/O port addresses are divided among the on-board devices.These devices include:
•
ICH3
•
ISP2312 Fibre Channel controller
•
82546 Ethernet controller
•
SMSC LPC47B272 SIO
•
MCH
•
IPMC
Please refer to the respective device specifications for specific I/O address usage.
The MCH uses only I/O ports 0xCF8 and 0xCFC for PCI configuration cycle generation. These
registers were shown in
transactions to its attached PCI buses. The ISP2312 may be programmed to map its 256-byte bank
of registers to memory and/or I/O space.
Table 56
Documents"
document numbers.
Table 56.

I/O Address Cross-References

Device
ICH3
MCH
ISP2312
LPC47B272
IPMC
82546
96
Section 5.1.1
lists document references to I/O descriptions. Please refer to
for a list of the referenced documents and their complete titles, revisions, and
Document Title/Number
ICH3 EDS
E7501 MCH EDS
ISP2312 Design Guide
LPC47B27x Datasheet
Intel IPMC EDS
Developer's Manual, OR2941
Description
and Section 5.1.2. The P64H2 forwards applicable I/O
Section/Page/Table
Section 7.3, Table A2 and A3
Section 4.3.5 and 4.3.6
Section 6.6.9 and 6.7
(Throughout datasheet)
Section 4.3.7
Section 3.1.1.4
Appendix A, "Reference
Technical Product Specification
Order #273817