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Intel NetStructure MPCBL0001 Technical Product Specification

Intel high performance single board computer technical product specifications
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Intel NetStructure
MPCBL0001
High Performance Single Board
Computer
Technical Product Specification
May 2006
Order Number: 273817-010

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Summary of Contents for Intel NetStructure MPCBL0001

  • Page 1 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Technical Product Specification May 2006 Order Number: 273817-010...
  • Page 2 INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.

  • Page 3: Table Of Contents

    Intel NetStructure Contents Introduction...13 Document Organization ...13 Glossary...14 Features Overview ...16 Application ...16 Functional Description ...16 2.2.1 Low Voltage Intel 2.2.2 Chipset...19 2.2.2.1 Intel 2.2.2.2 Intel 2.2.2.3 Intel 2.2.3 Memory (J8, J9, J10, J11) ...21 2.2.3.1 Memory Ordering Rule for the MCH ...21 2.2.4...
  • Page 4 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents E-Keying ... 46 IPMC Firmware Code ... 46 IPMC Firmware Upgrade Procedure ... 47 3.6.1 IPMC Firmware Upgrade Using KCS Interface ... 47 3.6.2 IPMC Firmware Upgrade via the IPMB Interface (RMCP)... 48 3.6.2.1...
  • Page 5 Intel NetStructure 3.16.1 Using Serial Port Buffering ...73 3.16.1.1 Configuring the Serial Port...73 3.16.1.2 Configuration of Buffering/Filtering ...76 3.16.1.3 Reading Buffered Data ...76 3.16.1.4 Examples ...77 Connectors ...80 Backplane Connectors...84 4.1.1 Power Distribution Connector (Zone 1)...84 4.1.2 Data Transport Connector (Zone 2)...85 4.1.3...
  • Page 6 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Legacy USB Support ... 112 BIOS Updates... 112 7.7.1 Language Support ... 113 Recovering BIOS Data ... 113 Boot Options ... 113 7.9.1 CD-ROM and Network Boot ... 113 7.9.2 Booting without Attached Devices ...
  • Page 7 12.2.1 In-Target Probe (ITP)...162 Thermals...163 Component Technology ...164 Warranty Information ...165 15.1 Intel NetStructure® Compute Boards and Platform Products Limited Warranty ...165 15.2 Returning a Defective Product (RMA) ...165 15.3 For the Americas ...166 15.3.1 For Europe, Middle East, and Africa (EMEA) ...166 15.3.2 For Asia and Pacific (APAC)...166...
  • Page 8 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Certifications... 169 Agency Information—Class A... 170 18.1 North America (FCC Class A)... 170 18.2 Canada – Industry Canada (ICES-003 Class A) (English and French-translated) ... 170 18.3 Safety Instructions (English and French-translated)... 170 18.3.1 English ...
  • Page 9 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 12 Link Descriptors for E-Keying ...46 13 Reset BIOS Flash Type ...49 14 Set Fibre Channel Port Selection ...49 15 Get Fibre Channel Port Selection ...50 16 Get HW Fibre Channel Port Selection ...50 17 Set Control State ...51...
  • Page 10 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 62 Supervisor and User Password Functions ... 115 63 Function Key Escape Code Equivalents ... 115 64 BIOS Setup Program Menu Bar ... 116 65 BIOS Setup Program Function Keys ... 116 66 Main Menu ...
  • Page 11 24 Front Panel Dimensions – Non FC SKU (PMC and Connectors)...105 25 Front Panel Dimensions – Non-FC SKU (Screws and LED) ...106 ® 26 Low Voltage Intel Xeon™ Processor Heatsink...109 27 Jumper/Connector Locations...147 28 Connecting Digital Ground to Chassis Ground...150 29 SOL Block Diagram ...152...

  • Page 12: Revision History

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Revision History Date Revision May 2006 September 2005 September 2005 July 2005 April 2005 February 2005 November 2004 June 2004 January 2004 October 2003 Added information related to User Programmable LED and Lead Free information.

  • Page 13: Introduction

    Intel NetStructure Introduction Document Organization This document gives technical specifications related to the Intel NetStructure Performance Single Board Computer. The MPCBL0001 is designed following the standards of the Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high availability, switched network computing. This document is intended for support during system product development and while sustaining a product.

  • Page 14: Glossary

    Inter-IC [Integrated Circuit]. 2-wire interface commonly used to carry management data. ® Intel Boot Agent. The Intel Boot Agent is a software product that allows your networked client computer to boot using a program code image supplied by a remote server. ®...
  • Page 15 Intel NetStructure IPMB IPMC IPMI LPC Bus MTBF NEBS Node Board MPCBL0001 MPCBL0002 Node Slot Physical Port SMBus SMS, SMSC Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer Integrated Device Electronics. Common, low-cost disk interface. Intelligent Platform Management Bus. Physical 2-wire medium to carry IPMI.

  • Page 16: Features Overview

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Features Overview Application The Advanced Telecommunications Compute Architecture (AdvancedTCA) standards define open architecture modular computing components for carrier-grade, communications network infrastructure. The goals of the standards are to enable blade-based modular platforms to be: •...

  • Page 17: Block Diagram

    Intel NetStructure Figure 1. Block Diagram Optional 2.5” Optional 2.5” Hard Disk Drive Hard Disk Drive RJ-45 Standard RJ-45 Standard Serial Microsystems Corp. Serial Microsystems Corp. Port LPC47B272 Super I/O Port LPC47B272 Super I/O Port Port 528 MB/s Optional PCI 64/66...
  • Page 18 4X the bus frequency, resulting in peak data transfer rates up to 3.2 or 4.3 GBytes/s. In addition to the NetBurst microarchitecture, the Low Voltage Intel Xeon processor includes a groundbreaking technology called Hyper-Threading Technology Technology improves processor performance for multithreaded applications or multitasking environments by supporting multiple software threads on each processor.

  • Page 19: Intel ® E7501 Memory Controller Hub (U22)

    — Supports a 36-bit system bus addressing model — 12 deep in-order queue, two deep defer queue Note: The current MPCBL0001 is designed to run with the Intel processor frequency, the processor side bus (PSB) will run at 400 MT/s with a bandwidth of 3.2 GBytes/s.

  • Page 20: Intel ® 82801Ca I/O Controller Hub 3 (U7)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents • 16-bits wide, 66 MHz clock, 8x data transfer (octal pumped) • Supports 64-bit inbound, 32-bit outbound addressing The MCH I/O subsystems interface incorporates four hub interfaces. Each Hub interface is a point- to-point connection between the MCH and an I/O bridge/device.

  • Page 21: Memory (J8, J9, J10, J11)

    Intel NetStructure used. Even though the BIOS automatically sets the DMA mode/type, the OS could downgrade the DMA transfer mode. Check the operating system documentation to see what DMA mode is used by default and whether it is possible to change to a higher performance DMA mode.

  • Page 22: Super I/O (U28)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 2. Memory Ordering MCH, U22 2.2.4 2.2.4.1 Super I/O (U28) The Super I/O device (SIO) is an SMSC LPC47B272 enhanced Super I/O controller. The SIO connects to the ICH3 through its LPC bus connection. The SIO provides support for the front panel serial port (J17, see PS/2 ports.

  • Page 23: Real-Time Clock

    Intel NetStructure 2.2.4.2 Real-Time Clock The MPCBL0001 SBC real-time clock is integrated into the ICH3. It is derived from a 32.768 KHz crystal with the following specifications: • Frequency tolerance @ 25 ºC: ±20ppm • Frequency stability: maximum of -0.04ppm/(ΔºC) Aging ΔF/f (1...

  • Page 24: Fibre Channel* (U23) - Optional

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents • Supports advanced PCI commands such as MWI, MRM, and MRL, and PCI-X commands such as MRD, MRB, and MWB • Full IEEE 802.3ab auto-negotiation of speed, duplex, and flow-control configuration •...

  • Page 25: Pmc Connector (J25, J26, J27)

    Intel NetStructure • Support for JTAG boundary scan. • Supports IP as well as other protocols; however there are currently no plans to validate protocols other than SCSI_FCP. Each Fibre Channel interface of the ISP2312 includes its own internal 16-bit RISC processor and external 7.5 ns synchronous SRAM memory for instruction code and data.

  • Page 26: Fwh 0 (Main Bios)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Flash ROM BIOS updates can be performed by an end user or a network administrator over the LAN. The system should complete booting to an OS, MS-DOS* or logon to Linux* as root user.

  • Page 27: Onboard Power Supplies

    Intel NetStructure 2.2.7 Onboard Power Supplies The main power supply rails on the MPCBL0001 SBC are powered from dual-redundant -48 V power supply inputs from the backplane power connector (P10). There are also dual redundant, limited current, make-last-break-first (MLBF) power connections. See Layout (#1)”...

  • Page 28: Ipmb Standby Power

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents The VRM controller is designed to support multiple processor core voltages selected by the voltage identification (VID) pins on the processor. Logic provided on the SBC ensures that the VRM is not enabled if the two processors request different VID codes.

  • Page 29: Hardware Management Overview

    Intel NetStructure Hardware Management Overview The Intelligent Platform Management Controller (IPMC) is an Intel-designed baseboard management controller device manufactured by Philips Semiconductor* for Intel. The high-level architecture of the baseboard management for MPCBL0001 is represented in the block diagram below.

  • Page 30: Sensor Data Record (Sdr)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents The IPMC provides six I to the backplane while another one is used for communication with the ADM1026. The remaining buses are unused. If an IPMB bus fault or IPMC failure occurs, IPMB isolators are used to switch and isolate the backplane/system IPMB bus from the faulted SBC board.

  • Page 31: Hardware Sensors

    Intel NetStructure Table 2. Hardware Sensors (Sheet 2 of 3) Sensor Sensor Type Number Event Logging Disabled Voltage Voltage Temperature Processor Boot Error Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer Scanning Voltage/Signals Monitored Enabled Monitored...

  • Page 32: System Event Log (Sel)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 2. Hardware Sensors (Sheet 3 of 3) Sensor Sensor Type Number ACPI State System Event Voltage FRU Hot Swap IPMB Link Sensor SMI Timeout NOTE: The PROCHOT signal is a discrete signal but it is treated as a threshold sensor so that it can have a Sensor Type of Temperature.

  • Page 33: Sel Events Supported By The Mpcbl0001 Sbc

    Intel NetStructure Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 1 of 4) Sensor-Specific Sensor Sensor Offset (Event Type Type Code Data 1, Bit 0-3) Reserved Temperature 01h Voltage Processor Power Unit Memory NOTE: 1. These sensor offsets do not generate events, but they are valid offsets when reading the sensor values.
  • Page 34 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 2 of 4) Sensor-Specific Sensor Sensor Offset (Event Type Type Code Data 1, Bit 0-3) System Firmware Progress Event Logging...
  • Page 35 Intel NetStructure Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 3 of 4) Sensor-Specific Sensor Sensor Offset (Event Type Type Code Data 1, Bit 0-3) Critical Interrupt System ACPI Power state Watchdog Boot Error SMI Timeout E0h NOTE: 1.

  • Page 36: Temperature And Voltage Sensors

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 3. SEL Events Supported by the MPCBL0001 SBC (Sheet 4 of 4) Sensor-Specific Sensor Sensor Offset (Event Type Type Code Data 1, Bit 0-3) FRU Hot Swap IPMB Link...

  • Page 37: Sensor Thresholds For Ipmc Firmware 1.0

    Intel NetStructure Table 4. Sensor Thresholds for IPMC Firmware 1.0 Sensor Sensor Name Number +1.5 V +2.5 V +1.8 V VTT DDR (+1.25 V) +1.2 V +5 V -12 V +12 V CPU Core Voltage +3.3 V +1.8 VSB +3.3 VSB...

  • Page 38: Sensor Thresholds For Ipmc Firmware 1.2

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 5. Sensor Thresholds for IPMC Firmware 1.2 Sensor Sensor Name Description Number +1.5V +1.5V +2.5V +2.5V +1.8V +1.8V VTT DDR DDR Voltage +1.2V +1.2V -12V -12V +12V +12V CPU Core...

  • Page 39: Sensor Thresholds For Ipmc Firmware 1.7 And Above

    Intel NetStructure Table 6. Sensor Thresholds for IPMC Firmware 1.7 and Above Sensor Sensor Name Description Number +1.5V +1.5V +2.5V +2.5V +1.8V +1.8V VTT DDR DDR Voltage +1.2V +1.2V -12V -12V +12V +12V CPU Core CPU Core Voltage Voltage +3.3V +3.3V...

  • Page 40: Sensor Thresholds For Ipmc Firmware 1.14 And Above

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 7. Sensor Thresholds for IPMC Firmware 1.14 and Above Sensor Sensor Name Description Number +1.5V +1.5V +2.5V +2.5V +1.8V +1.8V VTT DDR DDR Voltage +1.2V +1.2V -12V -12V +12V...

  • Page 41: Processor Events

    Intel NetStructure 3.2.2 Processor Events The processor asserts IERR as the result of an internal error. A thermal trip error indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Upon THERMTRIP assertion, the IPMC powers down the boards.

  • Page 42: Pci Mapping For Hardware Component Subsystem

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 8 shows the PCI mapping of the component subsystem of the baseboard. Table 8. PCI Mapping for Hardware Component Subsystem Device 0XFF NOTE: This table is for MPCBL0001F04 boards. Bus Devices 5 and 7 do not exist for MPCBL0001N04 boards.

  • Page 43: System Acpi Power State

    Intel NetStructure 3.2.6 System ACPI Power State MPCBL0001 is targeted to support ACPI functionality, with support for the sleep states S0, S4 & S5. On assertion of ICH3_SLP_S5# and ICH3_SLP_S3# GPIOs, IPMC sends out a hot-swap event message to the shelf manager requesting deactivation. On successful reception of a deactivation message from the shelf manager, the FRU enters M1 power state and remains in this state.

  • Page 44: Port 80H Post Codes

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 9. CPU Failure Behavior CPU Failure Detection Operational Phase POST Runtime 3.2.10 Port 80h POST Codes When there is an FRB3 failure, the event message sent from the CPU Status sensor with sensor type code 07 provides the last Port 80 code byte written by the BIOS.

  • Page 45: Field Replaceable Unit (Fru) Information

    Following are the definitions for the multirecord implemented by the firmware as part of FRU data. Table 10. FRU Multirecord Data for CPU/RAM/PMC/BIOS Version Information Variable Manufacturer ID (Intel IANA number) Record Version Type/Length CPU Numbers Type/Length RAM Info...

  • Page 46: E-Keying

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents E-Keying E-Keying has been defined in the PICMG 3.0 Specification to prevent board damage, prevent misoperation, and verify fabric compatibility. The FRU data contains the board point-to-point connectivity record as described in Section 3.7.2.3 of the PICMG 3.0 Specification.

  • Page 47: Ipmc Firmware Upgrade Procedure

    Intel NetStructure When the firmware is commanded to enter firmware (FW) update mode, the operational code uses a special branch, Software Interrupt, to jump to the FW update code in the boot block. Once in FW update mode, the update code is copied into RAM, then the firmware jumps to the code in RAM to execute.

  • Page 48: Ipmc Firmware Upgrade Via The Ipmb Interface (Rmcp)

    Please refer to the latest IPMC firmware release notes for the upgrade procedure. The upgrade procedure, utility, and upgraded firmware are part of the IPMC firmware release package, which can be downloaded from the Intel web site at atca/index.htm. 3.6.2 IPMC Firmware Upgrade via the IPMB Interface (RMCP) Figure 5.

  • Page 49: Reset Bios Flash Type

    01h – Checksum failure Completion code NetFn = 3Ah (OEM Request) Cmd = 02h Intel IANA number (LSB) = 57h Intel IANA number = 01h Intel IANA number (MSB) = 00h Fibre Channel 1 setting, 0=disabled, 1=front panel, 2=Backplane, 3= Reserved, FF= Don’t change settings,...

  • Page 50: Get Hw Fibre Channel Port Selection

    This command sets the state of a control pin and overrides the control pin’s auto state. Refer to Table 20 page 52 NetFn = 3Ah (OEM Request) Cmd = 03h Intel IANA number (LSB) = 57h Intel IANA number = 01h Intel IANA number (MSB) = 00h Completion code Intel IANA number (LSB) = 57h...

  • Page 51: Set Control State

    Intel NetStructure Table 17. Set Control State NetFn/LUN Command Byte 1 Byte 2 Byte 1 Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer NetFn = 3Eh (OEM Request) Cmd = 20h Control number Control state, 0 = Deassert, 1 = Assert, 3 = Reserved, FF = Don’t change settings...

  • Page 52: Get Control State

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 3.7.6 Get Control State This command sets the state of a control pin. This command overrides the AUTO-state of the control pin. Refer to Table 18. Get Control State NetFn/LUN...

  • Page 53: Hot-Swap Process

    Intel NetStructure Hot-Swap Process The MPCBL0001 SBC has the ability to be hot-swapped in and out of a chassis. The onboard IPMC manages the SBC’s power-up and power-down transitions. The list below, along with Figure 6, illustrates this process. 1. Ejector latch is opened. HOT_SWAP_PB# assertion. IPMC firmware detects the assertion of this signal.

  • Page 54: Ejector Mechanism

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 3.9.1 Hot-Swap LED (DS10) The MPCBL0001 SBC supports one blue Hot Swap LED, mounted on the front panel. See Figure 14, “MPCBL0001NXX SBC Front Panel” on page 81 when it is safe to remove the SBC from the chassis. The on-board IPMC drives this LED to indicate the hot-swap state.

  • Page 55: Interrupts And Error Reporting

    Interrupts and Error Reporting 3.10.1 Device Interrupts The Low Voltage Intel mechanism for delivering interrupts that is slightly different from, though fully compatible with, previous IA-32 system platforms. The change affects only the delivery mechanism and no changes are required to existing software.

  • Page 56: Interrupt Signals

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 22. Interrupt Assignments (Sheet 2 of 2) Legacy Interrupt HI-B P64H2 BTINTR# HI-C P64H2 BTINTR# Fibre Channel INTA# Fibre Channel INTB# PMC INTA# PMC INTB# PMC INTC# PMC INTD#...

  • Page 57: Error Reporting

    Intel NetStructure 3.10.2 Error Reporting The MCH handles error reporting from the memory subsystem. Errors consist of correctable and uncorrectable bit errors. The ECC algorithms used are capable of correcting any number of bit errors contained within a 4-bit nibble. In addition, any number of bit errors contained within two 4- bit nibbles is detected.

  • Page 58: Acpi

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 3.11 ACPI ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer. The use of ACPI with theMPCBL0001 SBC requires an operating system that provides ACPI support.

  • Page 59: Reset Logic

    1. A power up of the SBC. The SMC enables the onboard power supplies. 2. The SMC negates the ICH3_PWROK signal (see Note below). 3. A “reset” command from the Port CF9h I/O register (refer to the “Intel Controller Hub 3 (ICH3-S) Datasheet” for information about this register).

  • Page 60: Warm Boot

    Panel” on page 81 2. A processor shutdown special cycle occurred. 3. An INIT command from Port 92h I/O register (refer to the Intel 3 (ICH3-S) Datasheet for information about this register). 4. An INIT command from Port CF9h I/O register.

  • Page 61: Cold Boot

    Intel NetStructure 3.12.5 Cold Boot Any soft reset that does not meet the configuration described in the preceding Warm Boot section is classified as a cold boot. Execution starts at the reset vector, and BIOS initializes and configures all devices, including memory subsystem, as if a hard reset had occurred. See Actions”...
  • Page 62 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents As the many voltages power up, each regulator produces a “power good” signal. All of these power good signals are logically OR’d (with the exception of the VRM power good) to produce the ICH3_PWROK signal input to the ICH3 as shown in is active, it indicates all on-board power is good.

  • Page 63: Reset Chain

    Intel NetStructure Figure 9. Reset Chain ICH3 Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer ICH3_PCIRST# FWH 0 FWH 1 H_CPURST E7501 DIMMs PCIRST A HI-B P64H2 PCIRST B PCIRST A HI-C PCIRST B P64H2 Super I/O...

  • Page 64: Wdt #1

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 3.13 Watchdog Timers (WDTs) Figure 10, “Watchdog Timers” on page 64 timers (WDTs) on the MPCBL0001 SBC. Figure 10. Watchdog Timers ICH3 (South Bridge) WDT #3 3.13.1 WDT #1 The first WDT (WDT #1) is a hardware timer in the IPMC. WDT #1 is IPMI compliant; its interaction with the host processor BIOS or system software is accomplished through IPMI commands over the Keyboard Controller Style (KCS) interface to the IPMC.

  • Page 65: Wdt #2

    Intel NetStructure WDT #1 can also be configured to take various actions before timing out (for example, SMI, NMI, nothing) or after timing out (for example, hard reset, power down, or power cycle). In addition, an event can be logged into the SEL whenever the watchdog timer expires. If WDT #1 expires, the IPMC is not reset.

  • Page 66: Led Status

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 3.14 LED Status 3.14.1 Health LED The MPCBL0001 SBC supports one bicolor health LED to indicate the SBC’s health status, i.e., whether a fault or error condition has been detected on the SBC. This LED is mounted on the front faceplate and driven by the onboard IPMC.

  • Page 67: Ide Drive Activity Led

    Intel NetStructure 3.14.4 IDE Drive Activity LED Table 28. IDE Drive Activity LED LED Status Green (Blinking) 3.14.5 User Programmable LEDs The MPCBL0001 SBC provides two bicolor LEDs for user-programmable functions. The LEDs can be driven to display a red, green or amber color. When these LEDs are lit, they indicate a status of a user-defined function.

  • Page 68: Network Link/Speed Leds

    LEDs. SDP[6] is connected to the Green LED, and SPD[7] is connected to the Red LED. Refer to the documentation for the Intel on how to drive these LED signals. Note that existing network drivers may drive these GPIO pins.

  • Page 69: Fibre Channel Port State Leds

    Intel NetStructure Table 33. Ethernet Controller Port State LED LED Status (L1 and L5) Red/Green/Amber NOTE: Refer to Figure 14 Front Panel. 3.14.8 Fibre Channel Port State LEDs The MPCBL0001 SBC supports two Fibre Channel port state LEDs mounted on the front faceplate.

  • Page 70: Fru Payload Control

    Specification. Through this command, the payload can be reset, rebooted, or have its diagnostics initiated. The FRU payload can be controlled by a command line via the Intel NetStructure Chassis Management Module (CMM). The following CMM commands are supported by the MPCBL0001.

  • Page 71: Diagnostic Interrupt

    NetFn=30h, Responder LUN=02h (SMS) 2’s complement of the previous byte (chk1) (varies) Board’s IPMB address (depends on slot) Sequence=01h, Requestor LUN=00h (IPMB) Intel’s command for shutdown/reboot Reboot action 2’s complement of the sum of the previous 4 bytes (chk2) Contents IPMB Interface...

  • Page 72: Serial Port Buffering Overview

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents The implementation details are as below: Figure 12. Diagnostic Interrupt Command Implementation (H_NMI) Asserts NMI signal 1. CMM sends a frucontrol=3 command to IPMC initiating a diagnostic interrupt. 2. When the IPMC receives frucontrol=3, it asserts the NMI signal to the CPU via the GPIO pins connected to the H_NMI pin.

  • Page 73: Using Serial Port Buffering

    Intel NetStructure Table 37. Escape Sequences Not Buffered with Filter Enabled Description Move cursor up 1 row Move cursor down 1 row Move cursor right 1 column Move cursor left 1 column Home Clear Display Screen Set cursor position to row;col.

  • Page 74: Set Serial/Modem Configuration Command: Net Function=0Ch, Command=10H

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 38. Set Serial/Modem Configuration Command: Net Function=0Ch, Command=10h Request Data Response Data Byte Data Field [7:4] – Reserved [3:0] – Channel number 4h = Serial channel Parameter Selector (Must be 07h)

  • Page 75: Get Serial/Modem Configuration Command: Net Function=0Ch, Command=11H

    Intel NetStructure Table 39. Get Serial/Modem Configuration Command: Net Function=0Ch, Command=11h Request Data Response Data Setting the Super I/O’s serial port parameters varies as to which part of the operational sequence is desired to be buffered: BIOS or system. BIOS message buffering must be configured from the BIOS Setup screen that deals with Remote Access.

  • Page 76: Configuration Of Buffering/Filtering

    3.16.1.2 Configuration of Buffering/Filtering Configuration of the Serial Buffering and Filtering features is accomplished with Intel-specific (OEM) IPMI commands: Set Serial Buffer Configuration and Get Serial Buffer Configuration. The Set Serial Buffer Configuration command can enable/disable both filtering and buffering.

  • Page 77: Examples

    Intel NetStructure There is an Intel-specific command to read back the buffer data in chunks of 16 bytes. This command requires a 16 bit offset into the buffer from which to read. System software can invoke this command several times in order to read the entire buffer. A buffer offset of 0 refers to the start of the oldest data in the buffer and not necessarily the physical start of the buffer.
  • Page 78 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents function PrintUsage() echo echo "Usage: $0 location" echo echo "Where: location = the location to read from (i.e. blade3, blade13, etc)" echo echo "This program reads the entire Serial Buffer from the selected location"...
  • Page 79 Intel NetStructure if [ $# -ne 1 ]; then PrintUsage LOC=$1 # Location to read from SEL_FILENAME="$LOC.txt" echo echo "Serial Buffer from $LOC will be saved as $SEL_FILENAME" echo rm -f $SEL_FILENAME declare val OFFSET_LSB=0 OFFSET_MSB=0 TOTAL_BYTES=0 while true; do # Read some bytes val=(`cmmset -l $LOC -d ipmicommand -v "0x30 0x30 0 $OFFSET_LSB $OFFSET_MSB"`)

  • Page 80: Connectors

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Connectors Connectors along the rear edge of AdvancedTCA server blades are divided into three distinct zones, as described in Section 2.3 of the PICMG 3.0 Specification. • Zone 1 for system management and power distribution •...

  • Page 81: Mpcbl0001Nxx Sbc Front Panel

    Intel NetStructure Figure 14. MPCBL0001NXX SBC Front Panel Ethernet Controller Port State: L1 Ethernet Controller Port State: L5 Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer Out of Service LED Health LEDs IDE Drive Activity Channel A...

  • Page 82: Mpcbl0001Fxx Sbc Front Panel

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 15. MPCBL0001FXX SBC Front Panel Ethernet Controller Port State: L1 Ethernet Controller Port State: L5 Out of Service LED Health LEDs IDE Drive Activity Channel A Network Link LEDs: L2...

  • Page 83: Led Descriptions

    Intel NetStructure Table 43. LED Descriptions IDE Drive Activity Table 44. Connector Assignments Backplane Connectors Mezzanine connector P1 Mezzanine connector P2 Positronic Power Connector Data Transport Connector (Zone 2) Front Panel Connectors USB Connector Serial Port Connector J25, 26, 27...

  • Page 84: Backplane Connectors

    5.55 Amperes are allocated to MPCBL0001 on the -48 VDC redundant power feeds. This is equivalent to 200 Watts at the minimum input voltage (-36 VDC). The Zone 1 connector and pin out is compatible with the backplane for Intel NetStructure Technical Product Specification.

  • Page 85: Data Transport Connector (Zone 2) J23

    Two 2 Gbit Fibre Channel ports on the extended fabric (two differential signal pairs each, eight signals total). The connector used is AMP/Tyco part number 1469001-1, Intel part number A66621-001. Figure 17, “Data Transport Connector (Zone 2) J23” on page 85 connector.

  • Page 86: Alignment Blocks

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents P[C]dxp where: P = Prefix (B=Base Interface [Gigabit Ethernet], F= Fabric Interface [Fibre Channel]) C = Channel (1-2) d = direction (Tx = Transmit, Rx = Receive) x = port number (0-1)

  • Page 87: Front Panel Connectors

    Intel NetStructure Front Panel Connectors 4.2.1 USB Connector (J12) MOLEX part Number: The MPCBL0001 SBC has one vertical USB connector that supports USB 1.1. USB connector JX is available at the front panel, as shown in page 80. The figure shows its position on the board. See Assignments”...

  • Page 88: Serial Port Connector (J17) Pin Assignments

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 18. Serial Port Connector (J17) Optional Top Ground Tabs Optional Side Ground tabs (2 places) Table 48. Serial Port Connector (J17) Pin Assignments Connector Pin Serial Port Signal Number...

  • Page 89: Db9 To Rj-45 Pin Translation

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 19. DB9 to RJ-45 Pin Translation Technical Product Specification Order #273817...

  • Page 90: Fibre Channel Small Form-Factor Pluggable (Sfp) Receptacle (J34 And J35)

    Fibre Channel CONNECTOR Pin # Rate Select (not implemented) 4.2.4 Fibre Channel SFP Optical Transceiver Module Refer to the Intel NetStructure transceivers that have been validated. The report can be downloaded from http://www.intel.com/design/network/products/cbp/atca/mpcbl0001.htm 1367073-1 for its position on the board. See for pinout information.

  • Page 91: Pmc Connectors (J25, J26, J27)

    Intel NetStructure Table 50. Fibre Channel SFP Pin Assignments USFibre Channel Connector (J34, J35) Pin Assignments Fibre Channel CONNECTOR Pin # Transmitter Fault (not supported) Receiver Inverted DATA Out Receiver Non-Inverted DATA Out Transmitter Non-Inverted DATA In Transmitter Inverted DATA In 4.2.5...

  • Page 92: Pmc Connector Pin Assignments - 32 Bit

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 51. PMC Connector Pin Assignments - 32 Bit Signal Ground INTB# BUSMODE1# INTD# Ground Ground REQ[0]# +3.3V (V I/O) AD[28] AD[25] Ground AD[22] AD[19] +3.3V (V I/O) FRAME# Ground...

  • Page 93: Pmc Connector Pin Assignments - 64 Bit

    Intel NetStructure Table 52. PMC Connector Pin Assignments - 64 Bit Signal PCI-RSVD Ground C/BE[6]# C/BE[4]# +3.3 V (V I/O) AD[63] AD[61] Ground AD[59] AD[57] +3.3 V (V I/O) AD[55] AD[53] Ground AD[51] AD[49] Ground AD[47] AD[45] +3.3 V (V I/O)

  • Page 94: On-Board Connectors

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents On-board Connectors 4.3.1 IDE Connector (J24) Table 53. IDE Connector Pin Assignments Pin # Signal Name Reset IDE Host Data 7 Host Data 6 Host Data 5 Host Data 4...

  • Page 95: Addressing

    Intel NetStructure Addressing Configuration Registers 5.1.1 Configuration Address Register MCH CONFIG_ADDRESS I/O Address: Default Value: Access: Size: CONFIG_ADDRESS is a 32-bit I/O register that can be accessed only as a Dword. A byte or word reference passes through the Configuration Address Register and hub link interface HI_A onto the PCI_A bus as an I/O cycle.

  • Page 96: I/O Address Assignments

    Device ICH3 ICH3 EDS E7501 MCH EDS ISP2312 ISP2312 Design Guide LPC47B272 LPC47B27x Datasheet IPMC Intel IPMC EDS 82546 Developer’s Manual, OR2941 Description Section 5.1.1 Section 5.1.2. The P64H2 forwards applicable I/O Document Title/Number Section/Page/Table Section 7.3, Table A2 and A3 Section 4.3.5 and 4.3.6...

  • Page 97: Memory Map

    Intel NetStructure Memory Map Table 57. Memory Map Memory Device Top of addressable memory Firmware Hub Devices (x2) -- Firmware Hub Device 0 -- Firmware Hub Device 1 HI-B P64H2 IOAPIC B HI-B P64H2 IOAPIC A HI-C P64H2 IOAPIC B...

  • Page 98: Ipmc Addresses

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents IPMC Addresses The IPMC supports 6 I The ADM1026 device is connected to SMBus 3 and provides voltage measurement capability and additional board configuration status. Table 58. SMBus Addresses 8-bit Address (W/R)

  • Page 99: Specifications

    Intel NetStructure Specifications This chapter defines the MPCBL0001 operating and nonoperating environments. It also documents the procedures followed to determine the reliability of MPCBL0001. Mechanical Specifications 6.1.1 Board Outline Figure 20 Figure 21 of major components. The board dimensions are 280 mm x 322.25 mm. The board pitch is 1.2”...

  • Page 100: Component Layout (#1)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 20. Component Layout (#1) IDE Connector (J24) NOTE: MAC Address 2 is an incremental value of MAC Address 1. 280 mm PMC Connectors Gigabit Ethernet ® Intel Xeon ™...

  • Page 101: Component Layout (#2)

    Intel NetStructure Figure 21. Component Layout (#2) Components Illustrated Above: A - IDE connector (J24) B - Power mezzanine card + cover C - PMC connectors D - Barcode: serial number + PBA version number E - DIMM banks F - EMI filter mezzanine G - Barcode: MAC Address 1 (Note: MAC Address 2 is an incremental value of MAC Address 1.

  • Page 102: Backing Plate

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 6.1.2 Backing Plate The MPCBL0001 SBC has a rugged metal backing plate that forms a single-piece face plate. This backing plate is made of 1.2 mm (0.048") steel which has been zinc post-plated to resist corrosion and rust.

  • Page 103: Front Panel Dimensions - Fc Sku (Pmc And Connectors)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 22. Front Panel Dimensions – FC SKU (PMC and Connectors) Technical Product Specification Order #273817...

  • Page 104: Front Panel Dimensions - Fc Sku (Screws And Leds)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 23. Front Panel Dimensions – FC SKU (Screws and LEDs) Technical Product Specification Order #273817...

  • Page 105: Front Panel Dimensions - Non Fc Sku (Pmc And Connectors)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 24. Front Panel Dimensions – Non FC SKU (PMC and Connectors) Technical Product Specification Order #273817...

  • Page 106: Front Panel Dimensions - Non-Fc Sku (Screws And Led)

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 25. Front Panel Dimensions – Non-FC SKU (Screws and LED) Technical Product Specification Order #273817...

  • Page 107: Environmental Specifications

    Standards Handbook – Telco Specification Document No. A78805-01. The test methodology is a combination of Intel and NEBs test requirements with the intent that the product will pass pure system-level NEBs testing. Intel will not be completing NEBs testing on the SBC. The following table summarizes environmental limits, both operating and nonoperating.

  • Page 108: Environmental Assumptions

    Xeon™ processors. Typical values were obtained by running the Windows* 2000*-based application “Drive Reaper” against networked shared drives. “Max” values were obtained by running Intel's DOS* based “Maxpower” utility, version 6.0. Note: A TriEMS card was installed for all power management tests. The TriEMS dissipates 550 mW typical.

  • Page 109: Cooling Requirements

    The weight of the baseboard (N04 and F04) is 3.0645 kg (6.75 lbs.) without any packaging materials. Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer ® MPCBL0001 High Performance Single Board Computer SBC should be Figure 26, “Low Voltage Intel ® Xeon™ Processor Heatsink Contents ® Xeon™ Processor Heatsink” on B0903-01...

  • Page 110: Bios Features

    BIOS Features Introduction The Intel NetStructure Intel/AMI BIOS, which is stored in flash memory and updated using a disk-based program. In addition to the BIOS and BIOS setup program, the flash memory contains POST and Plug and Play support. The BIOS displays a message during POST identifying the type of BIOS and a revision code. Refer to the specification update for the latest default settings.

  • Page 111: Redundant Bios Functionality

    Intel NetStructure The utility is part of the BIOS release package and can be downloaded from the Intel web site at http://www.intel.com/design/network/products/cbp/software/bios/mpcbl0001.htm. Chapter 10, “Operating the Unit,” Redundant BIOS Functionality MPCBL0001 hardware has two flash banks for BIOS where redundant copies are stored. BIOS bank selection logic is connected to the IPMC, and the IPMC firmware allows selection of the BIOS bank.

  • Page 112: Legacy Usb Support

    To install an operating system that supports USB, verify that Legacy USB support in the BIOS Setup program is set to Enabled and follow the operating system’s installation instructions. BIOS Updates The BIOS can be updated using either of the following utilities, which are available on the Intel Web site: •...

  • Page 113: Language Support

    Accordingly, if there is not a bootable CD in the CD-ROM drive, the system attempts to boot from the next defined drive. The network can be selected as a boot device. This Intel booting from the onboard LANs if connected to a network. Typically, MPCBL0001's Gigabit Ethernet is routed through the AdvancedTCA backplane to the front panel of an AdvancedTCA switch, which is then connected to a LAN.

  • Page 114: Fast Booting Systems

    Note: It is possible to optimize the boot process to the point where the system boots so quickly that the Intel logo screen (or a custom logo splash screen, if implemented) is be seen. Monitors and hard disk drives with minimum initialization times can also contribute to a boot time that might be so fast that necessary logo screens and POST messages cannot be seen.

  • Page 115: Remote Access Configuration

    Intel NetStructure Table 62. Supervisor and User Password Functions Password Set Supervisor Mode None Any user can change all options Supervisor and Can change all user options Supervisor only Can change all options User only Can't get into supervisor mode until user pass- word is cleared.

  • Page 116: Main Menu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents BIOS Setup Introduction The BIOS Setup program can be used to view and change the BIOS settings for the computer. The BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST) begins and before the operating system boot begins.

  • Page 117: Advanced Menu

    Intel NetStructure Table 66. Main Menu Feature BIOS ID Processor System Memory Size System Time System Date Advanced Menu To access this menu, select Advanced on the menu bar at the top of the screen. Main CPU Configuration IDE Configuration...

  • Page 118: Cpu Configuration Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 67 describes the Advanced menu. This menu sets advanced features that are available through the chipset. Table 67. Advanced Menu Feature CPU Configuration IDE Configuration SuperIO Configuration ACPI Configuration...

  • Page 119: Ide Configuration Submenu

    Intel NetStructure The submenu represented in the following table is used for configuring the CPU. Table 68. CPU Configuration Submenu Feature Manufacturer Brand String Frequency HyperThreading † Technology NOTE: Bold text indicates default setting. 8.3.2 IDE Configuration Submenu To access this submenu, select Advanced on the menu bar, then IDE Configuration.

  • Page 120: Primary Ide Master/Slave Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 69. IDE Configuration Submenu (Sheet 2 of 2) Feature Hard Disk Write Protect IDE Detect Time Out ATA(PI) 80Pin Cable Detect. NOTE: Bold text indicates default setting. 8.3.2.1 Primary IDE Master/Slave Submenu...

  • Page 121: Primary Ide Master/Slave Submenu

    Intel NetStructure Table 70. Primary IDE Master/Slave Submenu Feature Device Vendor Size LBA Mode Block Mode PIO Mode Async DMA Ultra DMA S.M.A.R.T Type LBA/Large Mode Block (Multi-Sector Transfer) PIO Mode DMA Mode S.M.A.R.T 32 Data Transfer ARMD Emulation Type NOTE: Bold text indicates default setting.

  • Page 122: Floppy Configuration Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 8.3.3 Floppy Configuration Submenu To access this submenu, select Advanced on the menu bar, then Floppy Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration...

  • Page 123: Superio Configuration Submenu

    Intel NetStructure 8.3.4 SuperIO Configuration Submenu To access this submenu, select Advanced on the menu bar, then SuperIO Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG)

  • Page 124: Acpi Configuration Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 8.3.5 ACPI Configuration Submenu To access this submenu, select Advanced on the menu bar, then ACPI Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration Advanced ACPI Configuration...

  • Page 125: Advanced Acpi Configuration Submenu

    Intel NetStructure 8.3.5.1 Advanced ACPI Configuration Submenu To access this submenu, select Advanced on the menu bar, then ACPI Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration Advanced ACPI Configuration System Management Configuration Event Logging Configuration...

  • Page 126: System Management Configuration Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 8.3.6 System Management Configuration Submenu To access this submenu, select Advanced on the menu bar, then System Management Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration...

  • Page 127: Event Logging Configuration Submenu

    Intel NetStructure 8.3.7 Event Logging Configuration Submenu To access this submenu, select Advanced on the menu bar, then Event Logging Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG)

  • Page 128: Fibre Channel Routing (Picmg) Configuration Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 8.3.8 Fibre Channel Routing (PICMG) Configuration Submenu To access this submenu, select Advanced on the menu bar, then Fibre Channel Routing (PICMG) Configuration. Main CPU Configuration IDE Configuration Floppy Configuration...

  • Page 129: Remote Access Configuration Submenu

    Intel NetStructure 8.3.9 Remote Access Configuration Submenu To access this submenu, select Advanced on the menu bar, then Remote Access Configuration. Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG)

  • Page 130: Usb Configuration Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 78. Remote Access Configuration Submenu (Sheet 2 of 2) Feature VT-UTF8 Combo Key Support SOL Support NOTES: 1. Bold text indicates default setting. 2. This support is only available and introduced in BIOS P13-0028 or above.
  • Page 131 Intel NetStructure Table 79. USB Configuration Submenu USB Mass Storage Reset Delay USB Beep Message NOTE: Bold text indicates default setting. Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer 10 sec 20 sec Number of seconds POST waits for USB mass storage device after unit command.

  • Page 132: Usb Mass Storage Device Configuration

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 8.3.10.1 USB Mass Storage Device Configuration Main CPU Configuration IDE Configuration Floppy Configuration SuperIO Configuration ACPI Configuration System Management Configuration Event Logging Configuration Fibre Channel Routing (PICMG) Remote Access Configuration...

  • Page 133: Boot Menu

    Intel NetStructure USB Configuration USB Mass Storage Device Configuration PCI Configuration The menu represented in the following table is used to configure USB options. Table 81. PCI Configuration Submenu Feature Onboard Fibre Channel Onboard Gigabit LAN Boot Menu To access this menu, select Boot from the menu bar at the top of the screen.

  • Page 134: Boot Device Priority Submenu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents The menu represented in the following table is used to configure Boot Settings. Table 83. Boot Settings Configuration Submenu Feature Quick Boot Quiet Boot AddOn ROM Display Mode Bootup Num-Lock...

  • Page 135: Hard Disk Drive Submenu

    Intel NetStructure Table 84. Boot Device Priority Submenu Feature Boot Device Boot Device Last Boot Device NOTE: A device only shows as an option if it is installed and detected by the BIOS during boot. 8.4.3 Hard Disk Drive Submenu To access this submenu, select Boot on the menu bar, then Hard Disk Drive Priority.

  • Page 136: Security Menu

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 86. OS Load Timeout Timer Submenu Feature OS Load Timeout OS Load Action Security Menu To access this menu, select Security from the menu bar at the top of the screen.

  • Page 137: Exit Menu

    Intel NetStructure The menu represented in the following table is for exiting the BIOS Setup program, saving changes, and loading and saving defaults. Table 88. Exit Menu Feature Save Changes and Exit Discard Changes and Exit Discard Changes Load Optimal Defaults...

  • Page 138: Bios Error Messages

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Error Messages BIOS Error Messages The following table lists the error messages. Table 89. BIOS Error Messages Error Message Timer Error This timer is based on 8254 resides in ICH-3. Error message indicates an error while programming the count register of the timer.

  • Page 139: Bootblock Initialization Code Checkpoints

    Intel NetStructure 2. Clear CMOS Jumper enabled 3. MFG Jumper installed. Port 80h POST Codes During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred.

  • Page 140: Post Code Checkpoints

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 91. POST Code Checkpoints (Sheet 1 of 2) Checkpoint Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the kernel variable.
  • Page 141 Intel NetStructure Table 91. POST Code Checkpoints (Sheet 2 of 2) Checkpoint Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system. Mid POST initialization of chipset registers.

  • Page 142: Acpi Runtime Checkpoints

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 92. DIM Code Checkpoints Checkpoint Initializes different buses and performs the following functions: • Function 0: Reset, Detect, and Disable - Disables all device nodes, PCI devices, and PnP ISA cards. Assigns PCI bus numbers.

  • Page 143: Bios Configuration

    Intel NetStructure Operating the Unit 10.1 BIOS Configuration Chapter 7, “BIOS Features,” information about using the BIOS Setup program. See the MCH” on page 21 10.2 BIOS Image Updates At times, new BIOS images will be released to add additional features to the SBC. The release package contains the flash utility, which comes in two versions.

  • Page 144: Saving Bios.bin To The Sbc

    4. Upon completion, perform a reset to ensure the new CMOS settings and BIOS are loaded. Caution: To ensure that the BIOS.bin file is not corrupted, Intel strongly suggests performing these steps before major deployment of any SBCs running in a live network environment.

  • Page 145: Bios Utility Command Line Options

    Intel NetStructure Table 96. Suggested Method of BIOS Image Synchronization prior to BIOS Upgrade BIOS Image FWH0 FWH0 Image N Image N FWH1 FWH1 Image N-1 Image N-1 FWH0 FWH0 Image N Image N FWH1 FWH1 Image N Image N...

  • Page 146: Flashdos Utility Command Line Options

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 97. Flashdos Utility Command Line Options Command Line Parameter /b [option] bios_image where possible [option] values are: • /z - do not clear the CMOS • /zc - update the CMOS from image...

  • Page 147: Jumpers

    Intel NetStructure 10.4 Jumpers The MPCBL0001 contains several jumper posts that allow the user to configure certain options not configurable through the BIOS Setup Utility. The “Jumper Locations” figure below shows the placement of the MPCBL0001 jumpers. See for the function of each jumper.

  • Page 148: J18 Pin Assignments

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Table 98. J18 Pin Assignments Lattice* Compatible JTAG Header 1 +3.3 VSB TDI (H0_SKTOCC#) ISPEN# Key - no pin or connection 11 TMS (H1_SKTOCC#) 13 GND 15 TCK (WDT_EN) NOTE: Processors must be removed before using the Lattice JTAG interface.

  • Page 149: Digital Ground To Chassis Ground Connectivity

    Intel NetStructure Table 101. J40 Jumper Assignments Jumper J40-1 to 2 Boot block unprotected. J40-2 to 3 IPMC Boot block has been protected (Default). If user were to update the IPMC boot block, the jumper needs to be connected to 1-2.

  • Page 150: Connecting Digital Ground To Chassis Ground

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Figure 28. Connecting Digital Ground to Chassis Ground Insulated screw Technical Product Specification Order #273817...

  • Page 151: References

    197.pdf 11.2 SOL Architecture The SOL implementation on the Intel NetStructure in Section 15 of the IPMI v2.0 specification. Serial over LAN (SOL) enables suitably designed blades and servers to transparently redirect serial character stream of a baseboard UART to/from a remote client via LAN over RMCP+ sessions.

  • Page 152: Sol Block Diagram

    3. Client software running on any remote node that has LAN access to the blade whose serial port data is to be accessed. The IPMC is responsible for controlling the serial hardware MUX, the C/SMBus/IPMB connections that ® Intel NetStructure MPCBL0001 Technical Product Specification...

  • Page 153: Architectural Components

    (From BIOS setup menu) Disabled Enabled Enabled Enabled Note: x = does not matter ® Intel NetStructure MPCBL0001 Technical Product Specification Figure 29, the IPMI controller on the blade provides a UART SOL Support IPMC request Front Panel (From BIOS...

  • Page 154: Theory Of Operation

    This allows network redirection of blade’s serial port data stream independent of the host OS or BIOS. The Ethernet controller plays a critical role in redirecting the packets meant for the IPMC, based on receive filters. ® Intel NetStructure MPCBL0001 Technical Product Specification http://support.intel.com/ for further...

  • Page 155: Utilities

    It is important to note that while ipmitool is a supported utility, reference_cfg is provided as an unsupported reference to be modified at will by customers to suit their specific environments and integration needs. ® Intel NetStructure MPCBL0001 Technical Product Specification Serial Over Lan (SOL)

  • Page 156: Supported Usage Model

    ID and password to authenticate access • channel, user, payload, and SOL privilege levels The configuration utility is referring to the reference_cfg script described above. RMCP Connection (over LAN) ® Intel NetStructure MPCBL0001 Technical Product Specification Blade A Blade B Blade C...

  • Page 157: Installation And Configuration

    When running the reference script on a remote node over RMCP via a shelf manager, RMCP to IPMB bridging must be enabled on the shelf manager. If using the Intel NetStructure® MPCMM0001 Chassis Management Module Shelf Manager, then the cmdPrivillige.ini file included in the tar archive needs to be installed in the /etc directory of the Shelf Manager.

  • Page 158: Bios And Os Configuration

    To configure a blade for SOL communications, many configurations are required (for example, user information, channel parameters, LAN parameters, and SOL parameters). Most of the values used for configuration appear as hard-coded default values. http://ipmitool.sourceforge.net ® Intel NetStructure MPCBL0001 Technical Product Specification for more...

  • Page 159: Sol User Information

    11.7.2 SOL User Information Intel’s SBCs implement four different users, User1 through User4. User1 has null username which is not editable. The script configures User2. User2 is enabled and specifically enabled for SOL payloads. The user name is “solusername”, zero-padded to a length of 16 bytes as per the IPMI specification.

  • Page 160: Sol Parameters

    “help” - display usage, version number and a list of options. When this option is specified, all other options are ignored. “location” - specifies which blade to configure. When running on an Intel NetStructure MPCMM0001 Chassis Management Module (CMM), this value should be one of [“blade1”...“blade14”].

  • Page 161: Executing The Sol Client (Ipmitool)

    IPMC settings as set by the SOL configuration reference script. 11.8 Operating Environment The SOL client utility supports the following operating system environments: • MontaVista* Carrier Grade Linux* (CGE 3.1) ® Intel NetStructure MPCBL0001 Technical Product Specification Serial Over Lan (SOL)

  • Page 162: Supervision

    Intel continually looks for ways to maximize the development and delivery of mission-critical tools to our internal validation teams and strategic OEM customers. As a result, Intel has put together a third-party vendor program team which works with third-party vendors to develop and deliver specific tools formerly supplied by Intel to internal and external customers.

  • Page 163: Thermals

    Intel NetStructure Thermals The pressure drop curves versus the flow rate in This information is provided in accordance with Section 5 of the PICMG 3.0 Specification. It will aid the system integrator in using the MPCBL0001 SBC in various AdvancedTCA shelves.

  • Page 164: Component Technology

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Component Technology The main components implemented on the Intel NetStructure Single Board Computer are listed in the table below. Table 106. Main Components Code Name LP Prestonia ICH3 P64H2 Plumas 533...

  • Page 165: Returning A Defective Product (Rma)

    If the product is found to be otherwise defective, Intel, at its option, will replace or repair the product at no charge except as set forth below, provided that you deliver the product along with a return material authorization (RMA) number (see below) either to the company from whom you purchased it or to Intel.

  • Page 166: For The Americas

    Return Material Authorization (RMA) credit requests e-mail address: Direct Return Authorization (DRA) repair requests e-mail address: DRA on-line form: Intel Business Link (IBL): Telephone No.: 1-800-INTEL4U or 480-554-4904 Office Hours: Monday - Friday 0700-1700 MST Winter / PST Summer 15.3.1...
  • Page 167 If the Customer Support Group verifies that the product is defective, they will have the Direct Return Authorization/Return Material Authorization Department issue you a DRA/RMA number to place on the outer package of the product. Intel cannot accept any product without a DRA/RMA number on the package. Limitation of Liability and Remedies...

  • Page 168: Customer Support

    Intel NetStructure 16.2 Technical Support and Return for Service Assistance For all product returns and support issues, please contact your Intel product distributor or Intel Sales Representative for specific information. 16.3 Sales Assistance If you have a sales question, please contact your local Intel NetStructure Sales Representative or the Regional Sales Office for your area.

  • Page 169: Certifications

    Order #273817 ® MPCBL0001 High Performance Single Board Computer ® MPCBL0001 High Performance Single Board Computer has the following ® MPCBL0001N04 Single Board Computer and Intel NetStructure ® MPCBL0001F04Q Single Board Computer and Intel NetStructure Contents ® for specific details.

  • Page 170: Agency Information-Class A

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Agency Information—Class A 18.1 North America (FCC Class A) FCC Verification Notice This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

  • Page 171: French

    Intel NetStructure -This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode conductor is connected. -This equipment shall be located in the same immediate area (such as adjacent cabinets) as any other equipment that has a connection between the earthed conductor of the same DC supply circuit and the earthing conductor, and also the point of earthing of the DC system.

  • Page 172: Japan Vcci Class A

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 18.5 Japan VCCI Class A 18.6 Korean Class A 18.7 Australia, New Zealand Technical Product Specification Order #273817...

  • Page 173: Agency Information-Class B

    Intel NetStructure Agency Information—Class B 19.1 North America (FCC Class B) FCC Verification Notice This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

  • Page 174: Japan Vcci Class B

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents -This equipment shall be connected directly to the DC supply system earthing electrode conductor or to a bonding jumper from an earthing terminal bar or bus to which the DC supply system earthing electrode conductor is connected.

  • Page 175: Korean Class B

    Intel NetStructure 19.5 Korean Class B 19.6 Australia, New Zealand Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer Contents...

  • Page 176: Safety Warnings

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Safety Warnings Caution: Review the following precautions to avoid personal injury and prevent damage to this product or products to which it is connected. To avoid potential hazards, use the product only as specified.

  • Page 177: Mesures De Sécurité

    Intel NetStructure Warning: Avoid electric shock: Do not operate in wet, damp, or condensing conditions. To avoid electric shock or fire hazard, do not operate this product with enclosure covers or panels removed. Warning: Avoid electric shock: For units with multiple power sources, disconnect all external power connections before servicing.
  • Page 178 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Pour les systèmes C.A., utilisez uniquement un câble d'alimentation avec une prise de terre et établissez toujours les connexions à une prise secteur mise à la terre. Chaque câble d'alimentation doit être connecté...

  • Page 179: Sicherheitshinweise

    Intel NetStructure ventilateur ou les conduits de l'unité. Des boucliers ou des panneaux de gestion de l'air doivent être installés dans les connecteurs inutilisés du châssis. Les spécifications environnementales peuvent varier d'un produit à un autre. Veuillez-vous reporter au manuel de l'utilisateur pour déterminer les exigences en matière de flux d'air et d'autres spécifications environnementales.
  • Page 180 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Das Gehäuse verfügt über einen eigenen Erdungs-Verbindungsbolzen. Stellen Sie die Erdungsverbindung her, ehe Sie das Stromkabel oder Peripheriegeräte anschließen, und trennen Sie die Erdungsverbindung niemals, so lange Strom- und Peripherieverbindungen angeschlossen sind.

  • Page 181: Norme Di Sicurezza

    Intel NetStructure Vorsicht: Lithiumbatterien. Bei unsachgemäßem Austausch oder Umgang mit Batterien besteht Explosionsgefahr. Zerlegen Sie die Batterie nicht und laden Sie diese nicht wieder auf. Entsorgen Sie die Batterie nicht durch Verbrennen. Beim Auswechseln der Batterie muss dasselbe oder ein der Händlerempfehlung gleichwertiges Modell verwendet werden (CR2032).
  • Page 182 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents NORME DI SICUREZZA PER LE UNITÀ MONTATE IN UN RACK. Questa unità può essere alloggiata in modo permanente in un rack. Il montaggio in rack deve essere conforme ai requisiti di resistenza fisica delle norme NEBS GR-63-CORE e NEBS GR 487.Prima di installare o rimuovere l'unità...

  • Page 183: Instrucciones De Seguridad

    Intel NetStructure 20.4 Instrucciones de Seguridad Examine las instrucciones sobre condiciones de seguridad que siguen para evitar cualquier tipo de daños personales, así como para evitar perjudicar el producto o productos a los que esté conectado. Para evitar riesgos potenciales, utilice el producto únicamente en la forma especificada.
  • Page 184 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Advertencia: Evite sobrecargas eléctricas, calor y riesgos de descarga eléctrica o incendio: Conecte el sistema sólo a un circuito de alimentación que tenga el régimen apropiado, según lo especificado en el manual de usuario del producto. No realice conexiones con terminales cuya capacidad no se ajuste al régimen especificado para ellos.

  • Page 185: Chinese Safety Warning

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents 20.5 Chinese Safety Warning Technical Product Specification Order #273817...

  • Page 186: Reference Documents

    The following documents should be available when using this specification. Documents that are not available on websites may be obtained from your IBL (Intel Business Link) account, or contact your Intel Field Sales Engineer (FSE) or Field Application Engineer (FAE).
  • Page 187 Intel NetStructure • Low Pin Count (LPC) Interface Specification industry/lpc.htm) ® • Intel Boot Agent. manual.htm) • Intel’s AdvancedTCA product line Technical Product Specification Order #273817 ® MPCBL0001 High Performance Single Board Computer (http://developer.intel.com/design/chipsets/ (http://www.intel.com/support/network/adapter/pro100/bootagent/ http://developer.intel.com/technology/atca/ Contents...
  • Page 188 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Contents Technical Product Specification Order #273817...

  • Page 189: List Of Supported Commands (Ipmi V1.5 And Picmg 3.0)

    Intel NetStructure List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 108. IPMI 1.5 Supported Commands (Sheet 1 of 3) Command Get Device ID Cold Reset Get Self Test Results Broadcast "Get Device ID" Command Reset Watchdog Timer Set Watchdog Timer...
  • Page 190 ® Intel NetStructure MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 108. IPMI 1.5 Supported Commands (Sheet 2 of 3) Command Set Event Receiver Get Event Receiver Platform Event (Event Message) Command...
  • Page 191 Intel NetStructure Table 108. IPMI 1.5 Supported Commands (Sheet 3 of 3) Command Run Initialization Agent Command Get SEL Info Get SEL Allocation Info Reserve SEL Get SEL Entry Add SEL Entry Partial Add SEL Entry Delete SEL Entry Clear SEL...

  • Page 192: Picmg 3.0 Ipmi Supported Commands

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer List of Supported Commands (IPMI v1.5 and PICMG 3.0) Table 109. PICMG 3.0 IPMI Supported Commands Command Get PICMG Properties Get Address Info FRU Control Get FRU LED Properties Get LED Color Properties...
  • Page 193 Intel NetStructure Table 110. IPMI 2.0 Supported Commands (Continued) Command Set User Name Get User Name Command Set User Password Command Activate Payload Deactivate Payload Get Payload Activation Status Get Payload Instance Info Set User Payload Access Get User Payload Access...

  • Page 194: Material Declaration Data Sheets

    ® Intel NetStructure MPCBL0001 High Performance Single Board Computer Material Declaration Data Sheets Material Declaration Data Sheets The following pages provide the Material Declaration Data Sheets for the following: • Intel NetStructure • Intel NetStructure ® MPCBL0001 Single Board Compute - MPCBL0001N04Q ®...
  • Page 195 * Quantity limit of 0.01% by mass (100 PPM) of homogeneous material for: Cadmium Intel understands RoHS requires: Lead and other materials banned in RoHS Directive are either (1) below all applicable substance thresholds as defined by the EU or (2) an approved exemption applies. (Note: RoHS implementation details are not fully defined and may change.)

  • Page 196: Technical Product Specification

    5. The remainder of this package consists of non-reportable metals (e.g., tin, iron, etc), epoxy resin and other non-metal materials. INTEL ACCEPTS NO DUTY TO UPDATE THIS MDDS OR TO NOTIFY USERS OF THIS MDDS OF UPDATES OR CHANGES TO THIS MDDS.
  • Page 197 * Quantity limit of 0.01% by mass (100 PPM) of homogeneous material for: Cadmium Intel understands RoHS requires: Lead and other materials banned in RoHS Directive are either (1) below all applicable substance thresholds as defined by the EU or (2) an approved/pending exemption applies. (Note: RoHS implementation details are not fully defined and may change.)
  • Page 198 5. The remainder of this package consists of non-reportable metals (e.g., tin, iron, etc), epoxy resin and other non-metal materials. INTEL ACCEPTS NO DUTY TO UPDATE THIS MDDS OR TO NOTIFY USERS OF THIS MDDS OF UPDATES OR CHANGES TO THIS MDDS.

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