System Event Log (Sel) - Intel NetStructure MPCBL0001 Technical Product Specification

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Intel NetStructure MPCBL0001 High Performance Single Board Computer
Contents
Table 2. Hardware Sensors (Sheet 3 of 3)
Sensor
Number
82h
83h
1Ah
1Bh
1Ch
1Dh
8Ah
8Bh
E0h
NOTE: The PROCHOT signal is a discrete signal but it is treated as a threshold sensor so that it can have a
Sensor Type of Temperature. IPMI does not have a discrete sensor type for temperatures. The
advantage of the PROCHOT sensor acting as a temperature sensor is that the CMM can recognize
events from this sensor as temperature events and adjust fan speed accordingly.
3.2

System Event Log (SEL)

The SEL is the collection of events that are generated by the IPMC. Event logs are stored in non-
volatile memory. This resides on the board and allows better tracking of error conditions on the
baseboard when it is moved from chassis to chassis. Having the SEL and logging functions
managed by the IPMC helps ensure that post-mortem logging information is available should a
failure occur that disables the systems processor(s). In the MPCBL0001, flash memory for IPMI
firmware can store up to 3276 SEL entries. Management software running on the host processor is
responsible for ensuring that SEL storage has sufficient space for SEL logging. Events are
normally forwarded to shelf manager and logged to SEL on the board. If SEL storage on the board
is full, new events are forwarded to the Shelf Manager but are not logged in to SEL on the board.
A set of IPMI commands (see
the SEL to be read and cleared and allows events to be added to the SEL. The IPMI commands
used for adding events to the SEL are Platform Event Message, Add SEL entry, and Partial Add
Entry. Table 3, "SEL Events Supported by the MPCBL0001 SBC" on page 33
events. Event Messages can be sent to the IPMC via the IPMB. This provides the mechanism for
satellite controllers to detect events and log them into the SEL.
32
Voltage/Signals
Sensor Type
Monitored
ACPI State ACPI State
System Event System Event
+12 V
-12 V
CPU Core Voltage
Voltage +1.5 V
FRU Hot Swap FRU State
IPMB Link Sensor Operational state of
IPMB-0
SMI Timeout Steady state
assertion of the SMI
line
Table 108, "IPMI 1.5 Supported Commands" on page
Scanning
Monitored Enabled
via under Power
State
IPMC Power On/
Off
IPMC Power On
ADM 1026 Power On
ADM 1026 Power On
ADM 1026 Power On
ADM 1026 Power On
IPMC Power On/
Off
Logical Power On/
Off
IPMC Power On
Technical Product Specification
Health LED
(Green to Red)
No change
No change
Exceeds critical
threshold
Exceeds critical
threshold
Exceeds critical
threshold
Exceeds critical
threshold
No change
No change
SMI Line asserted
(Offset bit 01h asserted)
189) allows
lists supported SEL
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