Chipset Features Setup - SOYO SY-K7VIA User Manual

BIOS Setup Utility

3-4.1 CHIPSET FEATURES SETUP

CHIPSET
FEATURES
Bank 0/1, 2/3,
4/5 DRAM
Timing
SDRAM Cycle
Length
Bank
Interleave
DRAM Clock
Memory Hole
P2C/C2P
Concurrency
Fast R-W
Turn Around Enabled
Setting Description
SDRAM This item allows you to select the
8/10ns value in this field, depending on
whether the board has paged
Normal
DRAMs or EDO (extended data
Medium
output) DRAMs.
Fast
Turbo
2 When synchronous DRAM is
3 installed, the number of clock
cycles of CAS latency depends on
the memory timing. Do not reset
this field from the default value
specified by the system designer.
4Way
This item controls SDRAM bank
interleave functionality. Setting to
Disabled
4 way gives the best performance.
2Way
Host Clock
This item allows you to control the
HCLK+33M
DRAM speed.
HCLK-33M
Disabled
Enabled Some interface cards will map
their ROM address to this area. If
this occurs, select [Enabled] in this
field.
Disabled This item allows you to
enable/disable the PCI to CPU,
Enabled
CPU to PCI concurrency
Disabled This item controls the DRAM
timing. It allows you to enable/
disable the fast read/write turn
around.
64
SY-K7VIA
Note
Default
Default
Default
Default
Default
Default
Default