SOYO SY-K7VIA User Manual page 15

Motherboard Description SY-K7VIA
PCI) that are synchronous/ pseudo-synchronous to the CPU bus. The chip
also contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels(doublewords) of post write buffers are
included to allow for concurrent CPU and PCI opeation. For PCI master
operation, forty-eight levels (doublewords) of post write buffers and
sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports
enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-
Mulitple and Memory-Write-Invalid commands to minimize snoop
overhead. In addition, advanced features are supported such as snoop
ahead, snoop filtering, L1/L2 write-bank forward to PCI master, and
L1/L2 write-bank merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. Delay transaction and read
caching mechanisms are also implemented for further improvement of
overall system performance.
The 352-pin Ball Grid Array VT82C686A PCI to ISA bridge supports four
levels (doublewords) of line buffers, type F DMA transfers and delay
transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant).
The VT 82C686A also includes an integrated keyboard controller with
PS2 mouse support, integrated DS12885 style real time clock with
extended 256 byte COMS RAM, integrated master mode enhanced IDE
controller with full scatter/ gather capability and extension to Ultra-DMA-
33/66 for 33/66 MB/sec transfer rate, integrated USB interface with root
hub and four function ports with built-in physical layer transceivers,
Distributed DMA supports, and OnNow/ ACPI compliant advanced
configuration and power management interface. The VT82C686A also
includes and Ac97/ MC97 link for interface to external audio and modem
codecs, and all "Super-I/O" functions (serial ports, parallel port, and
floppy drive interface and game port).
For sophisticated power management, KX133 provides independent clock
stop control for the CPU/SDRAM, PCI, and AGP buses and Dynamic
CKE control for powering down of the SDRAM. A separated suspend-
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