Chipset - SOYO SY-K7VIA User Manual

Motherboard Description SY-K7VIA
automatically detects if ECC memory is installed and provides the Setup
option for selecting ECC mode. If any non-ECC memory is installed, the
Setup option for ECC configuration does not appear and ECC operation is
not available.

1-9 CHIPSET

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VT8371
The KX133 chip set consists of the VT8371 system controller (516 pin
BGA) and the VT82C686A PCI to ISA bridge (352 pin BGA). The system
controller provides superior performance between. the CPU, DRAM, AGP
bus, and PCI bus with pipelined, burst, and concurrent operation.
The VT8371 supports eight banks of DRAMs up to 2.0GB. The DRAM
controller supports standard Synchronous DRAM(SDRAM) and Virtual
Channel SDRM (VC SDRAM), in a flexible mix/ match manner. The
Synchronous DRAM interface allows zero wait state bursting between the
DRAM and the data buffers at 66/100/133MHz. The eight banks of
DRAM can be composed of an arbitrary mixture of
1M/2M/4M/8M/16M/32MxN DRAMs. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit detection)
or EC(error checking) capability separately selectable on a bank-by-bank
basis.
The VT8371 system controller also supports full AGP v2.0 capability for
maximum bus utilization including 1x, 2x and 4x mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An
eight level request queue plus a four level post-write request queue with
thirty-two and sixteen quadwords of read and write data FIFO's
respectively are included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible CPU/
AGP/PCI remapping control is also provided for operation under protected
mode operating environments. Both Windows-95 VXD and Windows-98
/Windows 2000 miniport drivers are supported for interoperability with
major AGP-based 3D and DVD-capable multimedia accelerators.
The VT8371 supports two 32-bit 3.3/5V system buses (one AGP and one
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