SOYO SY-K7VIA User Manual page 71

BIOS Setup Utility
CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES
PCI Delay
Transaction
PCI#2 Access
#1 Retry
AGP Master 1
WS Write
AGP Master 1
WS Read
Memory
Parity/ECC
Check
Setting Description
Disabled The chipset has an embedded 32-bit
posted write buffer to support delay
Enabled
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
Disabled When disabled, PCI#2 will not be
disconnected until access finishes
Enabled
(default). When enabled, PCI#2 will
be disconnected if max retries are
attempted without success.
Disabled
Enabled When Enabled, writes to the
AGP(Accelerated Graphics Port) are
executed with one wait states.
Disabled
Enabled When Enabled, read to the AGP
(Accelerated Graphics Port) are
executed with one wait states.
Disabled
Enabled This item enabled when the system
detects memory parity and Error
Checking & Correcting.
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SY-K7VIA
Note
Default
Default
Default
Default
Default