Omron CQM1 Operation Manual page 151

response format
response monitoring time
Restart Bit
result word
retrieve
retry
return
reversible counter
reversible shift register
right-hand instruction
rightmost (bit/word)
rising edge
ROM
rotate register
RS-232C interface
RUN mode
rung
scan
scan time
scheduled interrupt
SCP
seal
self diagnosis
Glossary
A format specifying the data required in a response to a data transmission.
The time a device will wait for a response to a data transmission before assum-
ing that an error has occurred.
A bit used to restart part of a PC.
A word used to hold the results from the execution of an instruction.
The processes of copying data either from an external device or from a storage
area to an active portion of the system such as a display buffer. Also, an output
device connected to the PC is called a load.
The process whereby a device will re-transmit data which has resulted in an
error message from the receiving device.
The process by which instruction execution shifts from a subroutine back to the
main program (usually the point from which the subroutine was called).
A counter that can be both incremented and decremented depending on the
specified conditions.
A shift register that can shift data in either direction depending on the specified
conditions.
See terminal instruction.
The lowest numbered bits of a group of bits, generally of an entire word, or the
lowest numbered words of a group of words. These bits/words are often called
least-significant bits/words.
The point where a signal actually changes from an OFF to an ON status.
Read only memory; a type of digital storage that cannot be written to. A ROM
chip is manufactured with its program or data already stored in it and can never
be changed. However, the program or data can be read as many times as
desired.
A shift register in which the data moved out from one end is placed back into the
shift register at the other end.
An industry standard for serial communications.
The operating mode used by the PC for normal control operations.
See instruction line.
The process used to execute a ladder-diagram program. The program is
examined sequentially from start to finish and each instruction is executed in
turn based on execution conditions.
See cycle time.
An interrupt that is automatically generated by the system at a specific time or
program location specified by the operator. Scheduled interrupts result in the
execution of specific subroutines that can be used for instructions that must be
executed repeatedly at a specified interval of time.
See subtract count input.
See self-maintaining bit.
A process whereby the system checks its own operation and generates a warn-
ing or error if an abnormality is discovered.
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