Front Panel Video; 3.13 I/O Slots; X16 Riser Slot Definition; Pe Width Strapping - Intel S5500WB Technical Product Specification

Intel® Server Board S5500WB TPS
Onboard Video
Dual Monitor Video
3.12.3

Front Panel Video

®
The Intel Server Board S5500WB provides a mechanism to support video to the front panel via
the use of an internal header. When a monitor is plugged into the front panel video connector,
the rear panel video stream is disconnected.
There is a jumper option to change this default action. When the internal header is used by a
third-party Management card to do KVM over LAN and then when a monitor is plugged into the
rear panel video connector, the video stream to the internal header is cut off.

3.13 I/O Slots

3.13.1

X16 Riser Slot Definition

Slot 6 was defined to support riser cards. Slot 6 has a x16 physical connector with a PCI
Express* Gen II x8 electrical interface. Two clocks are provided so the bus can be bifurcated
into two x4 connectors.
Because of CPU placement, a 1U system supports only PCI Express* adapters that meet the
PCI SIG half card definition. Full-length boards are supported in a 2U system by using a taller
riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated.
Appendix A documents the pin assignments for this connector.
3.13.2

PE WIDTH Strapping

®
On the Intel Server Board S5500WB, the IOH needs to be informed of the PCI Express* bus
width during power on. This is accomplished using the PEWIDTH input straps. The mechanism
used is the PEWIDTH bits, one bit is used to signify the width and number of PCI Express*
buses used by the riser. For slot 6, the PEWIDTH bit used is 0.
1U one x8
2U two x4
By using this mechanism for selecting PCI Express* port width, you can avoid a BIOS
rediscover and reboot.
Revision 1.3

Table 10. Dual Video Options

Enabled
Disabled
Enabled
Disabled

Table 11. PEWIDTH Strapping Bits

Riser
1 x8 PCI Express* Slot
2 X4 PCI Express* Slots
Intel order number E53971-004
Shaded if onboard video is set to "Disabled"
Description
Functional Architecture
PEWIDTH0
pin A50
0
1
35