Intel S5500WB Technical Product Specification page 105

A dual socket server
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Intel® Server Board S5500WB TPS
QuickPath Interconnect (QPI)
0xA0h
1
0
0xA1h
1
0
0xA2h
1
0
0xA3h
1
0
0xA4h
0
1
0xA5h
0
1
0xA6h
1
0
0xA7h
1
0
0xA8h
1
0
0xA9h
1
0
0xAAh
0
1
0xABh
1
0
0xACh
1
0
0xADh
1
0
0xAEh
1
0
0xAFh
0
1
Integrated Memory Controller (IMC)
0xB0h
0
1
0xB1h
0
1
0xB2h
0
1
0xB3h
0
1
0xB4h
0
1
0xB5h
0
1
0xB6h
0
1
0
1
0xB7h
0
1
0xB8h
0
1
0xB9h
0
1
0xBAh
1
0
0xBBh
1
0
0xBCh
0xBDh
1
0
0xBEh
0
1
0xBFh
1
0
PCI Bus
0x50h
0
1
0x51h
0
1
0x52h
0
1
0x53h
0
1
0x54h
0
1
0x55h
0
1
Revision 1.3
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
Intel order number E53971-004
0 QPI Initialization
1 QPI Initialization
0 QPI Initialization
1 QPI Initialization
0 QPI Initialization
1 QPI Initialization
QPI Initialization
0
1 QPI Initialization
0 QPI Initialization
1 QPI Initialization
0
QPI Initialization
1 QPI Initialization
0 QPI Initialization
1 QPI Initialization
0 QPI Initialization
1 QPI Initialization
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Memory Initialization of Integrated Memory Controller
1 Memory Initialization of Integrated Memory Controller
0 Enumerating PCI buses
1 Allocating resources to PCI buses
0 Hot Plug PCI controller initialization
1 Reserved for PCI bus
0 Reserved for PCI bus
1 Reserved for PCI bus
Appendix A: POST Code LED Decoder
91

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