SOYO SY-P4VGA User Manual page 51

BIOS Setup Utility
DRAM Control
DRAM Clock
DRAM Timing
SDRAM CAS
Latency
Bank Interleave
Precharge to
Active(Trp)
Active to
Precharge(Tras)
Active to CMD
(Trcd)
DRAM Command
Rate
DRAM Burst
Length
CPU read DRAM
Mode
Setting Description
By SPD This item allows you to control
the DRAM clock speed.
Manual
By SPD If enable the DRAM will auto
detect the DRAM timing.
Manual
3 When synchronous DRAM is
installed, the number of clock
2.5
cycles of CAS latency depends
2
on the DRAM timing. Do not
1.5
reset this field from the default
value specified by the system
designer.
Disabled Increase DRAM performance.
2 Bank
4 Bank
2T Increase DRAM performance.
3T
6T Increase DRAM performance.
7T
2T Increase DRAM performance.
3T
2T Command Increase DRAM performance.
1T Command
4 Increase DRAM performance.
8
Medium Increase DRAM performance.
Slow
Fast
47
SY-P4VGA
Note
Default
Default
Default
Default
Default
Default
Default
Default
Default
Default