Motorola M68000 User Manual page 77

Table 5-1.
Asserted on
Case Control Rising Edge
No. Signal of State
N
1 DTACK A
BERR NA
NA
HALT
2 A
DTACK
BERR NA
HALT A/S
3 DTACK X
A
BERR
NA
HALT
4 A
DTACK
BERR NA
HALT NA
5 DTACK X
A
BERR
A/S
HALT
6 DTACK A
BERR NA
HALT NA
LEGEND:
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
NA — Signal not asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
NOTE: All operations are subject to relevant setup and hold times.
The negation of BERR and HALT under several conditions is shown in Table 5-6. (DTACK
is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).
EXAMPLE B:
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
simultaneously to retry the error cycle (case 5).
2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
time as DTACK (case 3).
3. For an MC68010, return DTACK before data verification. If data is invalid, assert
BERR and HALT to retry the error cycle (case 6).
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
DTACK BERR
, , and
MC68000/MC68HC000/001
EC000/MC68008 Results
N+2
S Normal cycle terminate and continue.
NA
X
S Normal cycle terminate and halt.
NA Continue when HALT negated.
S
X Terminate and take bus error trap.
S
NA
S Normal cycle terminate and continue.
A
NA
X Terminate and retry when HALT
S removed.
S
S Normal cycle terminate and continue.
A
A
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HALT
Assertion Results
MC68010 Results
Normal cycle terminate and continue.
Normal cycle terminate and halt.
Continue when HALT negated.
Terminate and take bus error trap.
Terminate and take bus error trap.
Terminate and retry when HALT
removed.
Terminate and retry when HALT
removed.
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