STROBES
AND R/W
BR
BGACK
BG
CLK
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, IPL2-IPL0, and VPA
guarantees their recognition at the next falling edge of the clock.
10-18
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
35
33
38
Figure 10-7. Bus Arbitration Timing
(Applies To A ll Processors E xcept The MC68EC 000)
For More Information On This Product,
Go to: www.freescale.com
37A
37
46
34
39
36
MOTOROLA