Motorola M68000 User Manual page 166

CLK
FC2–FC0
A23–A0
AS
LDS / UDS
R/W
DTACK
DATA IN
BERR / BR
(NOTE 2)
HALT / RESET
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the
next falling edge of the clock.
2. BR need fall at this time only to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 V and 2.0 V.
Figure 10-12. MC68EC000 Read Cycle Timing Diagram
10-26 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
S0 S1 S2 S3
6A
8
6
7
15
11
13
11A
17
9
18
48
47
32
56
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S4 S5 S6 S7
14
47
27
31
47
47
32
47
12
28
29
30
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