Motorola M68000 User Manual page 115

Table 7-13. Miscellaneous Instruction Execution Times
ANDI to CCR
ANDI to SR
EORI to CCR
EORI to SR
EXG
EXT
LINK
MOVE to CCR
MOVE to SR
MOVE from SR
MOVE to USP
MOVE from USP
NOP
ORI to CCR
ORI to SR
RESET
RTE
RTR
RTS
STOP
SWAP
TRAPV (No Trap)
UNLK
+Add effective address calculation time for word operand.
Table 7-14. Move Peripheral Instruction Execution Times
Instruction
MOVEP
+Add effective address calculation time.
7.12 EXCEPTION PROCESSING EXECUTION TIMES
Table 7-15 lists the timing data for exception processing. The numbers of clock periods
include the times for all stacking, the vector fetch, and the fetch of the first instruction of
the handler routine. The total number of clock periods, the number of read cycles, and the
number of write cycles are shown in the previously described format. The number of clock
7-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
Instruction Register
32(6/0)
32(6/0)
32(6/0)
32(6/0)
10(2/0)
32(4/4)
18(4/0)
18(4/0)
10(2/0)
32(6/0)
32(6/0)
136(2/0)
40(10/0)
40(10/0)
32(8/0)
24(6/0)
Size Register
Word
Long
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Memory
—
—
—
—
—
8(2/0) —
—
18(4/0)+
18(4/0)+
16(2/2)+
8(2/0) —
8(2/0) —
8(2/0) —
—
—
—
—
—
—
4(0/0) —
8(2/0) —
8(2/0) —
—
Memory Memory
24(4/2)
32(4/4)
Register
24(6/0)
32(8/0)
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