Motorola M68000 User Manual page 59

PROCESSOR
GRANT BUS ARBITRATION
1) ASSERT BUS GRANT (BG)
ACKNOWLEDGE RELEASE OF
BUS MASTERSHIP
1) NEGATE BUS GRANT (BG)
REARBITRATE OR RESUME
PROCESSOR OPERATION
Figure 5-14. 2-Wire Bus Arbitration Cycle Flowchart
CLK
FC2–FC0
A23–A1
AS
LDS/ UDS
R/W
DTACK
D15–D0
BR
BG
BGACK
PROCESSOR
Figure 5-15. 3-Wire Bus Arbitration Timing Diagram
(Not Applicable to 48-Pin MC68008 or MC68EC000)
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
DMA DEVICE
For More Information On This Product,
Go to: www.freescale.com
REQUESTING DEVICE
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
OPERATE AS BUS MASTER
1) EXTERNAL ARBITRATION DETER-
MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
RELEASE BUS MASTERSHIP
1) NEGATE BUS REQUEST (BR)
PROCESSOR DMA DEVICE
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