BCLK
DRIVE TO
OUTPUTS(1)
INPUTS(2)
RSTI (3)
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
3. This timing is applicable to all parameters specified relative to the negation of the RESET signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Mode select setup time to RESET negated.
F. Mode select hold time from RESET negated.
Figure 10-2. Drive Levels and Test Points for AC Specifications
10-6
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
DRIVE
TO 2.4 V
1.5 V
A
0.5 V
B
2.0 V
VALID
OUTPUT n
0.8 V
DRIVE TO
2.4 V
DRIVE TO
0.5 V
E
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1.5 V
2.0
VALID
V
n + 1
OUTPUT
0.8 V
C
D
2.0 V
2.0 V
VALID
INPUT
0.8 V
0.8 V
2.0 V
F
2.0 V
0.8 V
MOTOROLA