Intel Xeon Processor E5-1600 Datasheet page 161

Electrical Specifications
Table 7-4. Signal Description Buffer Types (Sheet 2 of 2)
Signal
DDR3
DMI2
Intel QPI
Open Drain CMOS
PCI Express*
Reference
SSTL
Notes:
1. Qualifier for a buffer type.
Table 7-5. Signal Groups (Sheet 1 of 3)
Differential/Single
Ended
DDR3 Reference Clocks
Differential
DDR3 Command Signals
Single ended
DDR3 Control Signals
Single ended
DDR3 Data Signals
Differential
Single ended
DDR3 Miscellaneous Signals
Single ended
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
DDR3 buffers: 1.5 V and 1.35 V tolerant
Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express*
2.0 and 1.0 Signaling Environment AC Specifications.
Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect
signaling
Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant
PCI Express* interface signals. These signals are compatible with PCI Express* 3.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe* specification.
Voltage reference signal.
Source Series Terminated Logic (JEDEC SSTL_15)
Buffer Type
2
SSTL Output
2
SSTL Output
CMOS1.5v Output
2
CMOS1.5v Output
Reference Output
Reference Input
2
SSTL Input/Output
SSTL Input/Output
SSTL Input
2
CMOS1.5v Input
Description
Signals
DDR{0/1/2/3}_CLK_D[N/P][3:0]
DDR{0/1/2/3}_BA[2:0]
DDR{0/1/2/3}_CAS_N
DDR{0/1/2/3}_MA[15:00]
DDR{0/1/2/3}_MA_PAR
DDR{0/1/2/3}_RAS_N
DDR{0/1/2/3}_WE_N
DDR_RESET_C{01/23}_N
DDR{0/1/2/3}_CS_N[9:0]
DDR{0/1/2/3}_ODT[5:0]
DDR{0/1/2/3}_CKE[5:0]
DDR_VREFDQTX_C{01/23}
DDR_VREFDQRX_C{01/23}
DDR{01/23}_RCOMP[2:0]
DDR{0/1/2/3}_DQS_D[N/P][17:00]
DDR{0/1/2/3}_DQ[63:00]
DDR{0/1/2/3}_ECC[7:0]
DDR{0/1/2/3}_PAR_ERR_N
DRAM_PWR_OK_C{01/23}
1
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