Intel Xeon Processor E5-1600 Datasheet page 151

Signal Descriptions
Table 6-16. Power and Ground Signals (Sheet 2 of 2)
VTTD_SENSE
VSS_VTTD_SENSE
VCCD_01 and VCCD_23
VCCPLL
VSA
VSS
VTTA
VTTD
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
Signal Name Description
VTTD_SENSE and VSS_VTTD_SENSE provide an isolated, low
impedance connection to the processor I/O power plane. These
signals must be connected to the voltage regulator feedback
circuit, which insures the output voltage (that is, processor
voltage) remains within specification. Please see the applicable
platform design guide for implementation details.
Variable power supply for the processor system memory interface.
Provided by two VRM/EVRD 12.0 compliant regulators per CPU
socket. VCCD_01 and VCCD_23 are used for memory channels 0,
1, 2, and 3 respectively. The valid voltage of this supply (1.50 V or
1.35 V) is configured by BIOS after determining the operating
voltages of the installed memory. VCCD_01 and VCCD_23 will also
be referred to as VCCD.
Note: The processor must be provided VCCD_01 and VCCD_23
for proper operation, even in configurations where no
memory is populated. A VRM/EVRD 12.0 controller is
recommended, but not required.
Fixed power supply (1.8V) for the processor phased lock loop
(PLL).
Variable power supply for the processor system agent units. These
include logic (non-I/O) for the integrated I/O controller, the
integrated memory controller (iMC), the Intel QPI agent, and the
Power Control Unit (PCU). The output voltage of this supply is
selected by the processor, using the serial voltage ID (SVID) bus.
Note: VSA has a Vboot setting of 0.9V. Refer to the VR12/IMVP7
Pulse Width Modulation Specification .
Processor ground node.
Combined fixed analog and digital power supply for I/O sections of
the processor Intel QPI interface, Direct Media Interface Gen 2
(DMI2) interface, and PCI Express* interface. These signals will
also be referred to as VTT. Please see the appropriate Platform
Design Guide (PDG)for implementation details.
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