Cmos And Open Drain Signals; Signal Characteristics; Signal Reference Voltages - Intel E8200 - Cpu Core 2 Duo 2.66Ghz Fsb1333Mhz 6M Lga775 Tray Datasheet

3. The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See
4. PROCHOT# signal type is open drain output and CMOS input.
.
Table 9.

Signal Characteristics

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
NOTES:
1. Signals that do not have R
Table 10.

Signal Reference Voltages

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
NOTE:
1. See
2.7.2

CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See
timing requirements for entering and leaving the low power states.
26
Signals with R
TT
1
Open Drain Signals
, nor are actively driven to their high-voltage level.
TT
GTLREF
Table 12 for more information.
Section 2.7.3 for the DC specifications. See
Section 6.1 for details.
Signals with No R
A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/
NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,
STPCLK#, TDO, TESTHI[12,10:0],
THERMTRIP#, VID[7:0], GTLREF[1:0], TCK,
TDI, TMS, TRST#, VTT_SEL
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
1
PWRGOOD , SMI#, STPCLK#, TCK
1 1
TDI , TMS , TRST#
Section 6.2
Electrical Specifications
TT
V /2
TT
1
,
1
for additional
Datasheet