Notes On Using Bus Operation Stop Bit (Halt = 1) - Fujitsu F2MCTM-16LX Hardware Manual

21.4.4

Notes on Using Bus Operation Stop Bit (HALT = 1)

The bus operation stop bit is set by writing to the bit, hardware reset and the node
status. The stop operation of the bus operation is different according to the state of the
message buffer.
Conditions for Setting Bus Operation Stop (HALT=1)
There are 3 conditions for setting bus operation stop (HALT = 1):
• After hardware reset
• When node status changed to bus off
• By writing 1 to HALT
Notes:
• The bus operation should be stopped by writing 1 to HALT before the F
power consumption mode (stop mode and timebase timer mode). If transmission is in progress when 1 is
written to HALT, the bus operation is stopped (HALT = 1) after transmission is terminated. If reception
is in progress when 1 is written to HALT, the bus operation is stopped immediately (HALT = 1). If
received messages are being stored in the message buffer (x), stop the bus operation (HALT = 1) after
storing the messages.
• To check whether the bus operation has stopped, always read the HALT bit.
Conditions for Canceling Bus Operation Stop (HALT = 0)
The condition for canceling the bus operation if halt is writing 0 to HALT.
Notes:
• Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is
performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input
to the receive input pin (RX) (HALT = 0).
• Canceling the bus operation stop when the node status is changed to bus off as above conditions is
performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have been input
128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and receive error
counters reach 0 and the node status is changed to error active.
• When write 0 to HALT during the node status is Bus Off, ensure that 1 is written to this bit.
State during Bus Operation Stop (HALT = 1)
• The bus does not perform any operation, such as transmission and reception.
• The transmit output pin (TX) outputs a High level (recessive bit).
• The values of other registers and error counters are not changed.
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
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MC-16LX is changed in low-
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