Hardware Interrupt Operation - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 3 INTERRUPTS
3.5.1

Hardware Interrupt Operation

An internal resource that has the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event that is unique to the internal resource occurs. When the interrupt enable
flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller compares the
interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that
request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request
with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined
by the hardware.
The CPU compares the received interrupt level (IL) and the ILM in the PS register. If the interrupt level is
smaller than the ILM value and the I bit of the PS register is set to '1', the CPU activates the interrupt
processing microcode after the currently executing instruction is completed. The CPU refers the ISE bit of
the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that the
ISE bit is 0 (interrupt), and activates the interrupt processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area
indicated by SSB and SSP, fetches 3 bytes of interrupt vector, loads them onto PC and PCB, updates the
ILM of PS to a level value of the received interrupt request, sets the S flag, then performs branch
processing. As a result, the interrupt processing program defined by the user is executed next.
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