Notes About Reset Cause Bits - Fujitsu F2MCTM-16LX Hardware Manual

Notes about Reset Cause Bits

Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via
the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are
both set to "1".
Power-on reset
For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the
software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1".
Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
corresponding to a reset cause that has already been generated is not cleared even though another reset is
generated (a setting of "1" is retained).
Note:
If the power is turned on under conditions where no power-on reset occurs, the value in WDTC register
may not be guaranteed.
CHAPTER 7 RESETS
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