Test Access Port (Tap) Connection - Intel BX80623I32100 Datasheet

Table 7-3. Signal Groups (Sheet 2 of 2)
Signal Group
PCI Express*
Differential
Differential
Single Ended
DMI
Differential
Differential
®
Intel FDI
Single Ended
Differential
Single Ended
Notes:
1. Refer to
2. SA and SB refer to DDR3 Channel A and DDR3 Channel B.
3. The maximum rise/fall time for UNCOREPWRGOOD is 20 ns.
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least 10 BCLKs with a maximum Trise/Tfall of 6 ns for the processor to recognize
the proper signal state. See
7.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.6-
2003 standards. Some small portion of the I/O pins may support only one of these
standards.
78
1
Type
Sense Points
Other
PCI Express Input
PCI Express Output
Analog Input
DMI Input
DMI Output
FDI Input
FDI Output
Analog Input
Chapter 6 and Chapter 8 for signal description details.
Section 7.10
Electrical Specifications
Signals
VCC_SENSE, VSS_SENSE, VCCIO_SENSE,
VSS_SENSE_VCCIO, VAXG_SENSE, VSSAXG_SENSE
SKTOCC#, DBR#
PEG_RX[15:0], PEG_RX#[15:0], PE_RX[3:0],
PE_RX#[3:0]
PEG_TX[15:0], PEG_TX#[15:0], PE_TX[3:0],
PE_TX#[3:0]
PEG_ICOMP0, PEG_COMPI, PEG_RCOMP0
DMI_RX[3:0], DMI_RX#[3:0]
DMI_TX[3:0], DMI_TX#[3:0]
FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INT
FDI_TX[7:0], FDI_TX#[7:0]
FDI_COMPIO, FDI_ICOMPO
for the DC specifications.
Datasheet, Volume 1