Intel BX80623I32100 Datasheet page 5

4.2.5.1
4.2.5.2
4.2.5.3
4.2.5.4
4.3 Integrated Memory Controller (IMC) Power Management ........................................ 52
4.3.1 Disabling Unused System Memory Outputs ................................................ 52
4.3.2 DRAM Power Management and Initialization ............................................... 53
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.4 PCI Express* Power Management ........................................................................ 55
4.5 Direct Media Interface (DMI) Power Management .................................................. 55
4.6 Graphics Power Management .............................................................................. 56
4.6.1 Intel
(also known as CxSR) ............................................................................. 56
4.6.2 Intel
4.6.3 Graphics Render C-State ......................................................................... 56
4.6.4 Intel
4.6.5 Intel
4.7 Thermal Power Management ............................................................................... 57
5 Thermal Management .............................................................................................. 59
6 Signal Description ................................................................................................... 61
6.1 System Memory Interface Signals........................................................................ 62
6.2 Memory Reference and Compensation Signals ....................................................... 63
6.3 Reset and Miscellaneous Signals.......................................................................... 64
6.4 PCI Express*-Based Interface Signals .................................................................. 65
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6.5 Intel Flexible Display Interface (Intel
6.6 Direct Media Interface (DMI) Signals.................................................................... 66
6.7 Phase Lock Loop (PLL) Signals ............................................................................ 66
6.8 Test Access Points (TAP) Signals ......................................................................... 66
6.9 Error and Thermal Protection Signals ................................................................... 67
6.10 Power Sequencing Signals .................................................................................. 67
6.11 Processor Power Signals ..................................................................................... 68
6.12 Sense Signals ................................................................................................... 68
6.13 Ground and Non-Critical to Function (NCTF) Signals ............................................... 68
6.14 Processor Internal Pull-Up / Pull-Down Resistors.................................................... 69
7 Electrical Specifications ........................................................................................... 71
7.1 Power and Ground Lands.................................................................................... 71
7.2 Decoupling Guidelines ........................................................................................ 71
7.2.1 Voltage Rail Decoupling........................................................................... 71
7.3 Processor Clocking (BCLK[0], BCLK#[0]) .............................................................. 72
7.3.1 Phase Lock Loop (PLL) Power Supply......................................................... 72
7.4 V Voltage Identification (VID) .......................................................................... 72
CC
7.5 System Agent (SA) VCC VID ............................................................................... 76
7.6 Reserved or Unused Signals................................................................................ 76
7.7 Signal Groups ................................................................................................... 77
7.8 Test Access Port (TAP) Connection....................................................................... 78
7.9 Storage Conditions Specifications ........................................................................ 79
7.10 DC Specifications .............................................................................................. 80
7.10.1 Voltage and Current Specifications............................................................ 80
7.11 Platform Environmental Control Interface (PECI) DC Specifications........................... 86
7.11.1 PECI Bus Architecture ............................................................................. 86
7.11.2 DC Characteristics .................................................................................. 87
Datasheet, Volume 1
Package C0 .............................................................................. 51
Package C1/C1E ....................................................................... 51
Package C3 State...................................................................... 52
Package C6 State...................................................................... 52
Initialization Role of CKE ............................................................ 54
Conditional Self-Refresh ............................................................ 54
Dynamic Power-down Operation ................................................. 55
DRAM I/O Power Management .................................................... 55
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Rapid Memory Power Management (Intel
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Graphics Performance Modulation Technology (Intel
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Smart 2D Display Technology (Intel
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Graphics Dynamic Frequency.......................................................... 57
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RMPM)
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S2DDT) .................................. 56
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FDI) Signals ............................................. 65
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GPMT) .............. 56
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